Question regarding a clock divider algorithm

[michael6866]

Hi,

I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach:

1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001"
2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly.
3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6.
4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates:
clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6)

I understand the above solution works fine. What I don't understand is why it couldn't be as simple as:
clkd_div = DFF_R1 | DFF_F5

Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind?

Thanks,
Michael

 

[rickman]

On 12/11/2015 10:44 PM, michael6866 wrote:

Hi,

I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach:

1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001"
2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly.
3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6.
4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates:
clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6)

I understand the above solution works fine. What I don't understand is why it couldn't be as simple as:
clkd_div = DFF_R1 | DFF_F5

Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind?

I haven't analyzed the algorithm in detail, but it sounds like they
*are* attempting to approach a 50% duty cycle.

((DFF_R1|DFF_R2)|DFF_F1) will produce a pulse two clock cycles wide
starting on the rising edge of cycle 1. ((DFF_F5|DFF_F6)|DFF_R6) will
produce a pulse two clock cycles wide starting on the falling edge of
cycle 5. That is 4.5 clock cycles from rising edge of the first pulse
to the rising edge of the second pulse. The signals DFF_F1 and DFF_R6
are pulses that cover the transition of the other two inputs to those
pulses preventing a glitch. The duty cycle will be 4/9 or 44.4%, not
too far from 50%.

Just using DFF_R1 and DFF_F5 will give 4.5 cycles between rising edges
of the pulses, but the duty cycle will only be 2/9 or 22.2%.

--

Rick

 

[michael6866]

On Saturday, December 12, 2015 at 2:41:26 AM UTC-5, rickman wrote:

On 12/11/2015 10:44 PM, michael6866 wrote:
Hi,

I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach:

1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001"
2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly.
3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6.
4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates:
clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6)

I understand the above solution works fine. What I don't understand is why it couldn't be as simple as:
clkd_div = DFF_R1 | DFF_F5

Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind?

I haven't analyzed the algorithm in detail, but it sounds like they
*are* attempting to approach a 50% duty cycle.

((DFF_R1|DFF_R2)|DFF_F1) will produce a pulse two clock cycles wide
starting on the rising edge of cycle 1. ((DFF_F5|DFF_F6)|DFF_R6) will
produce a pulse two clock cycles wide starting on the falling edge of
cycle 5. That is 4.5 clock cycles from rising edge of the first pulse
to the rising edge of the second pulse. The signals DFF_F1 and DFF_R6
are pulses that cover the transition of the other two inputs to those
pulses preventing a glitch. The duty cycle will be 4/9 or 44.4%, not
too far from 50%.

Just using DFF_R1 and DFF_F5 will give 4.5 cycles between rising edges
of the pulses, but the duty cycle will only be 2/9 or 22.2%.

--

Rick

Hi Rick,

Thanks for your reply. I can see the duty cycle is close to 50%. But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)?

Michael

 

[KJ]

On Saturday, December 12, 2015 at 11:05:07 AM UTC-5, michael6866 wrote:

But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)?

Duty cycle is usually only important if the part receiving the signal has a minimum high or low pulse time requirement. Maybe you can meet the requirement with a 44% duty cycle, but not a 22% duty cycle as an example.

Kevin Jennings

 

[michael6866]

On Saturday, December 12, 2015 at 12:03:53 PM UTC-5, rickman wrote:

On 12/12/2015 11:05 AM, michael6866 wrote:
On Saturday, December 12, 2015 at 2:41:26 AM UTC-5, rickman wrote:
On 12/11/2015 10:44 PM, michael6866 wrote:
Hi,

I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach:

1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001"
2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly.
3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6.
4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates:
clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6)

I understand the above solution works fine. What I don't understand is why it couldn't be as simple as:
clkd_div = DFF_R1 | DFF_F5

Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind?

I haven't analyzed the algorithm in detail, but it sounds like they
*are* attempting to approach a 50% duty cycle.

((DFF_R1|DFF_R2)|DFF_F1) will produce a pulse two clock cycles wide
starting on the rising edge of cycle 1. ((DFF_F5|DFF_F6)|DFF_R6) will
produce a pulse two clock cycles wide starting on the falling edge of
cycle 5. That is 4.5 clock cycles from rising edge of the first pulse
to the rising edge of the second pulse. The signals DFF_F1 and DFF_R6
are pulses that cover the transition of the other two inputs to those
pulses preventing a glitch. The duty cycle will be 4/9 or 44.4%, not
too far from 50%.

Just using DFF_R1 and DFF_F5 will give 4.5 cycles between rising edges
of the pulses, but the duty cycle will only be 2/9 or 22.2%.

--

Rick

Hi Rick,

Thanks for your reply. I can see the duty cycle is close to 50%. But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)?

Oscillator outputs are never exactly 50%. Even on crystal oscillators
and such the duty cycle is often specified to be in the range of 45/55
to 55/45. To get closer to 50% you can use a 2x rate and divide by 2
with a FF, but even that will have some skew due to the asymmetry of the
drive.

Getting close to a 50% duty cycle can matter to some circuits depending
on how they are designed. If you can't get close to 50% then you need
to use a circuit independent of duty cycle.

You asked why that design was the way it was. I expect it was driving
something where the duty cycle mattered.

--

Rick

Thanks Rick (and Kevin and Gabor). The paper itself doesn't mention any other module it drives. It's only about the clock divider itself. But I think your explanation makes sense.

Michael

 

[rickman]

On 12/12/2015 11:05 AM, michael6866 wrote:

On Saturday, December 12, 2015 at 2:41:26 AM UTC-5, rickman wrote:
On 12/11/2015 10:44 PM, michael6866 wrote:
Hi,

I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach:

1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001"
2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly.
3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6.
4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates:
clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6)

I understand the above solution works fine. What I don't understand is why it couldn't be as simple as:
clkd_div = DFF_R1 | DFF_F5

Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind?

I haven't analyzed the algorithm in detail, but it sounds like they
*are* attempting to approach a 50% duty cycle.

((DFF_R1|DFF_R2)|DFF_F1) will produce a pulse two clock cycles wide
starting on the rising edge of cycle 1. ((DFF_F5|DFF_F6)|DFF_R6) will
produce a pulse two clock cycles wide starting on the falling edge of
cycle 5. That is 4.5 clock cycles from rising edge of the first pulse
to the rising edge of the second pulse. The signals DFF_F1 and DFF_R6
are pulses that cover the transition of the other two inputs to those
pulses preventing a glitch. The duty cycle will be 4/9 or 44.4%, not
too far from 50%.

Just using DFF_R1 and DFF_F5 will give 4.5 cycles between rising edges
of the pulses, but the duty cycle will only be 2/9 or 22.2%.

--

Rick

Hi Rick,

Thanks for your reply. I can see the duty cycle is close to 50%. But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)?

Oscillator outputs are never exactly 50%. Even on crystal oscillators
and such the duty cycle is often specified to be in the range of 45/55
to 55/45. To get closer to 50% you can use a 2x rate and divide by 2
with a FF, but even that will have some skew due to the asymmetry of the
drive.

Getting close to a 50% duty cycle can matter to some circuits depending
on how they are designed. If you can't get close to 50% then you need
to use a circuit independent of duty cycle.

You asked why that design was the way it was. I expect it was driving
something where the duty cycle mattered.

--

Rick

 

[Gabor Szakacs]

On 12/12/2015 12:09 PM, KJ wrote:

On Saturday, December 12, 2015 at 11:05:07 AM UTC-5, michael6866 wrote:
But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)?

Duty cycle is usually only important if the part receiving the signal has a minimum high or low pulse time requirement. Maybe you can meet the requirement with a 44% duty cycle, but not a 22% duty cycle as an example.

Kevin Jennings

It's also important if you use both clock edges like for DDR interfaces.
This 2/9 clock circuit is duty cyle dependent as well. Any input clock
deviation from 50% introduces jitter on the output clocks, since the
time from one edge to the next depends on opposite input clock edges.
If you wanted to take the output of this circuit and use both edges,
e.g. to multiply by 2/9 again, the output of that circuit will be
jittery even given a 50% input clock and no asymmetry in the clock
divider itself.

--
Gabor