Question pertaining to a project

[JB]

http://goo.gl/ZgNnK4

Above is the VHDL code I've attached relating to a small "Baseball Scoreboard" project. I'm fairly new to VHDL (~2 months) so bare with me when it comes to common practices (real world type stuff).

I'm trying to code this now so, for instance, when the baseball count is 3-BALLS and 1-STRIKE and when the next pitch is thrown is a BALL then both the balls and strikes get reset back to "000" and "00".

The code attached is working but without this feature. I've tried numerous things without any luck. The reset on the top-level is for a "hits" button. When a hit is produced this button resets the count (currently working).

Thank you in advanced.

 

[JB]

This is funny you mention the "button press" as the clock because I know it's not the right method. I actually used a clock input and had changed it based on a friend's input, but knew it looked funny.

Also, the fact I could not use both signal in my processes was another big issue and something I figured would have to be changed.

Well, thank you very much Gabor. Glad I actually came to some solution (and had the same thoughts as you). I will implement what you suggested.

Thanks again!

 

[Gabor]

On 11/27/2014 9:29 PM, JB wrote:

http://goo.gl/ZgNnK4

Above is the VHDL code I've attached relating to a small "Baseball Scoreboard" project. I'm fairly new to VHDL (~2 months) so bare with me when it comes to common practices (real world type stuff).

I'm trying to code this now so, for instance, when the baseball count is 3-BALLS and 1-STRIKE and when the next pitch is thrown is a BALL then both the balls and strikes get reset back to "000" and "00".

The code attached is working but without this feature. I've tried numerous things without any luck. The reset on the top-level is for a "hits" button. When a hit is produced this button resets the count (currently working).

Thank you in advanced.

The problem I see is that you are using the "button press"
for each outcome as a clock. In real world applications,
this has issues due to switch bouncing. However, supposing
you had a "bounceless" button, you still get into trouble
because you now *need* two processes (as you currently have)
in order to use these two "clocks" but at the same time
you can't assign balls (or strikes) in *both* of these
processes, at least for synthesizable code. It might be
possible to generate two signals when strike or ball
happen on full count, and use each signal as an asynchronous
reset to the other process. However this can get a bit messy.
The usual way to handle this sort of problem is to use a
free-running clock to sample the buttons. Then your
state logic can all be in the same process driven by
that clock's rising edge. You would use shift registers
to synchronize and delay each button press and use
bits from these shift registers to detect edges of the
button synchronous to the clock. Now with one process,
you can set or clear any number of signals on any button
event (as detected by looking at the S/R bits).

--
Gabor

 

[colin_toogood@yahoo.com]

Makes a change from a traffic light controller. For full marks you need to read up on metastability, your simulator will always work but real D types can't cope with the button being pressed exactly when the clock edge occurs.

Colin

 

[JB]

@Gabor

I'm kind of stumped on this one. I understand the shift register approach but don't see how I can get the correct outputs of "01" "11" and "001" "011" "111". Whenever I place a '1' on the button press in put I get a constant change of outputs either "00" "10" "11" "00" even if the button is not pressed. Hmm..

 

[JB]

--So this does exactly what I want it too without the feature I described to you prior. I was having a hard time implementing the shift registers. Here, I have the case statements but everything is now within one process block.
My idea was something like:

if tempstrikes <="11" then
tempballs<="000";

type of thing, in order to clear the balls count if another strike is thrown and causes an out. But, it's not going to work based on the other assignments within the case statements.


library IEEE;
use ieee.std_logic_1164.all;

entity Baseball_New is

port (button_strikes : in std_logic;
button_balls : in std_logic;
clk : in std_logic;
reset : in std_logic;
led_strikes : out std_logic_vector (1 downto 0);
led_balls : out std_logic_vector (2 downto 0)

);

end entity;
architecture Baseball_New_arch of Baseball_New is
signal tempstrikes : std_logic_vector (1 downto 0);
signal tempballs : std_logic_vector (2 downto 0);

begin

process (clk)

begin

if reset='1' then
tempstrikes <="00";
elsif clk'EVENT AND clk = '1' AND button_strikes ='1' then



case ( tempstrikes) is

when "00" => tempstrikes <="01";
when "01" => tempstrikes <="11";
when "10" => tempstrikes <="00";
when "11" => tempstrikes<="00";
when others => tempstrikes <="00";


end case;
end if;
end process;


led_strikes <= tempstrikes;



process (clk) is

begin
if reset='1' then
tempballs<="000";


elsif clk'EVENT AND clk='1' AND button_balls ='1' then


case (tempballs) is

when "000" => tempballs <="001";
when "001" => tempballs <="011";
when "010" => tempballs <="000";
when "011" => tempballs<="111";
when others => tempballs <= "000";
end case;

end if;
end process;
led_balls<=tempballs;

end Baseball_New_arch;

 

[JB]

**Nevermind, this still has two processes. My apologies.

 

[Gabor]

On 11/28/2014 3:34 PM, JB wrote:

@Gabor

I'm kind of stumped on this one. I understand the shift register approach but don't see how I can get the correct outputs of "01" "11" and "001" "011" "111". Whenever I place a '1' on the button press in put I get a constant change of outputs either "00" "10" "11" "00" even if the button is not pressed. Hmm..

OK, I have to say I have no idea what you're asking here.
I looked back at your code and you haven't updated the paste.org
page. So without seeing what you have now I really can't
comment or help. By the way, you can always paste the VHDL
code (at least the interesting bits) right into your post
here instead of using an ad-sponsored site. After all VHDL is
just text...

--
Gabor

 

[rickman]

On 11/28/2014 10:38 PM, JB wrote:
> **Nevermind, this still has two processes. My apologies.

You need to change the sensitivity list to include reset.

process (clk, reset)

Also, if you want to post your code here, you should remove the tabs and
replace with spaces. I believe you code is using something less than 8
spaces per tab while posting tabs here defaults to 8.

--

Rick

 

[colin_toogood@yahoo.com]

A few notes that will help you out.

1) You are trying to gate the clocks. Assuming you are expecting to learn to write code for an FPGA this is bad. Imagine you have an FPGA with 10,000 flip flops that all need a clock. Xilinx etc have put a lot of work into allowing a single clock to get to them all which is running at 100s of MHz. You can't put an AND gate (clock AND button press) on the clock input of a flip flop. The logic (LUT) in front of the flip flop will happily include feedback from the output of the same flip flop so that when it is clocked nothing changes (except on the occasions when it should, of course).
2) As a result of 1) you need the button press to exist for exactly one clock. VHDL code is always littered with
button1 <= button;
if button1='0' and button='1' then --button has just been pressed and i need to do something on this clock.
3) Someone said about having only one process, what they meant was probably have only one clk'event although most would write "rising_edge" instead. With the above in mind this is now possible.

Colin
(He's a beginner, lets not have a long discussion about whether synthesis would unwrap the gated clock and put it where it should be(not that I have ever tried)).

 

[rickman]

On 12/11/2014 9:58 AM, colin_toogood@yahoo.com wrote:

A few notes that will help you out.

1) You are trying to gate the clocks. Assuming you are expecting to learn to write code for an FPGA this is bad. Imagine you have an FPGA with 10,000 flip flops that all need a clock. Xilinx etc have put a lot of work into allowing a single clock to get to them all which is running at 100s of MHz. You can't put an AND gate (clock AND button press) on the clock input of a flip flop. The logic (LUT) in front of the flip flop will happily include feedback from the output of the same flip flop so that when it is clocked nothing changes (except on the occasions when it should, of course).

I'm not sure this is true. Tell me how the synthesis tool will
distinguish these two examples...

1)
elsif clk'EVENT AND clk = '1' AND button_strikes ='1' then
.
.
.
end if;

2)
elsif clk'EVENT AND clk = '1' then
if button_strikes ='1' then
.
.
.
end if;
end if;

I am no expert at how the tools work, but my understanding is the logic
is simplified (flattened) and then optimization happens. Is that wrong?

2) As a result of 1) you need the button press to exist for exactly one clock. VHDL code is always littered with
button1 <= button;
if button1='0' and button='1' then --button has just been pressed and i need to do something on this clock.

I believe you are describing edge detection, no? And in front of that
he will need a debounce circuit.


> 3) Someone said about having only one process, what they meant was probably have only one clk'event although most would write "rising_edge" instead. With the above in mind this is now possible.

Yeah, one clocked process to handle the outputs. We all know what
happens when you try to assign a single output from multiple processes.

Colin
(He's a beginner, lets not have a long discussion about whether synthesis would unwrap the gated clock and put it where it should be(not that I have ever tried)).

Sure, I won't argue the style issue. I agree the separate IF condition
for describing the edge sensitivity is best from a readability
standpoint. I can't say for sure about the clock gating.

I suspect the OP is gone, but perhaps he will return to glean a bit more
from this topic.

--

Rick

 

[colin_toogood@yahoo.com]

Rick

We will probably never know for certain, but from many years experience with new graduates it is my belief that he intended to gate the clock.

I had already posted in this thread about metastability and others had already talked about debouncing.

Colin