Question of '

[fl]

Hi,

VHDL grammar is still not easy to me. I see this line on a forum:


architecture lut of bit_count is
subtype lutin is std_logic_vector (3 downto 0);
subtype lutout is std_logic_vector (2 downto 0);
type lut00 is array (natural range 0 to 15) of lutout;
constant bitcount: lut00 := (
"000", "001", "001", "010",
"011", "010", "010", "011",
"001", "010", "010", "011",
"010", "011", "011", "100"
);

signal temp: std_logic_vector (2 downto 0);
begin
temp <= bitcount( TO_INTEGER ( unsigned (lutin(a&b&c&d) ) ) );
.....


it has an error:

Illegal type conversion to lutin (operand type is not known).


I know the correct answer is:
temp <= bitcount( TO_INTEGER ( unsigned (lutin'(a&b&c&d) ) ) );


but I don't know the detail rule on understanding it. Online search ' gives
predefined attribute. Obviously here is not an attribute. What function of '
is here?

Thanks,

 

[Jim Lewis]

I know the correct answer is:
temp <= bitcount( TO_INTEGER ( unsigned (lutin'(a&b&c&d) ) ) );


but I don't know the detail rule on understanding it. Online search ' gives
predefined attribute. Obviously here is not an attribute. What function of '
is here?

Here it is a type qualifier that identifies the type of the expression.
If a,b,c,d are all std_ulogic or std_logic, then you could have simplified this to:
temp <= bitcount( TO_INTEGER ( unsigned'(a&b&c&d) ) );



Jim

 

[rickman]

On 9/25/2015 10:25 AM, fl wrote:

Hi,

VHDL grammar is still not easy to me. I see this line on a forum:


architecture lut of bit_count is
subtype lutin is std_logic_vector (3 downto 0);
subtype lutout is std_logic_vector (2 downto 0);
type lut00 is array (natural range 0 to 15) of lutout;
constant bitcount: lut00 := (
"000", "001", "001", "010",
"011", "010", "010", "011",
"001", "010", "010", "011",
"010", "011", "011", "100"
);

signal temp: std_logic_vector (2 downto 0);
begin
temp <= bitcount( TO_INTEGER ( unsigned (lutin(a&b&c&d) ) ) );

Is "bitcount" supposed to actually be a bit count? It's not.
bitcount(4) should be "001", no?

--

Rick

 

[fl]

On Friday, September 25, 2015 at 11:50:31 AM UTC-4, rickman wrote:

On 9/25/2015 10:25 AM, fl wrote:
Hi,

VHDL grammar is still not easy to me. I see this line on a forum:


architecture lut of bit_count is
subtype lutin is std_logic_vector (3 downto 0);
subtype lutout is std_logic_vector (2 downto 0);
type lut00 is array (natural range 0 to 15) of lutout;
constant bitcount: lut00 := (
"000", "001", "001", "010",
"011", "010", "010", "011",
"001", "010", "010", "011",
"010", "011", "011", "100"
);

signal temp: std_logic_vector (2 downto 0);
begin
temp <= bitcount( TO_INTEGER ( unsigned (lutin(a&b&c&d) ) ) );

Is "bitcount" supposed to actually be a bit count? It's not.
bitcount(4) should be "001", no?

--

Rick

Rick:
You are right. The original code on the table of bitcount(4) and other
entries was wrong. Thanks,