Question about std_logic variable compared with '0'

[fl]

Hi,

I never took a VHDL class, although I read a book for some time. Recently I
have some progress. Some conceptual questions pop up occasionally. I find
understanding these questions help me writing good code. 'in2sel' is the
entity input port. I am curious about ( in2sel > '0' ). I guess in2sel should
be resolved to '1' or '0' (Otherwise 'X' 'Z' 'H' etc. have some pre-determined
order/priorities). Assume in2sel is resolved to '1'. What does '1' > '0' mean?
i.e. the comparing is on what category? Is it an integer subtype? Or something
else? I don't find the solution after a web search. Hopefully someone gives
me an interpretation or hint.


Thanks,


in2sel : IN std_logic;

in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed;

 

[rickman]

On 10/20/2015 10:38 PM, fl wrote:

Hi,

I never took a VHDL class, although I read a book for some time. Recently I
have some progress. Some conceptual questions pop up occasionally. I find
understanding these questions help me writing good code. 'in2sel' is the
entity input port. I am curious about ( in2sel > '0' ). I guess in2sel should
be resolved to '1' or '0' (Otherwise 'X' 'Z' 'H' etc. have some pre-determined
order/priorities). Assume in2sel is resolved to '1'. What does '1' > '0' mean?
i.e. the comparing is on what category? Is it an integer subtype? Or something
else? I don't find the solution after a web search. Hopefully someone gives
me an interpretation or hint.


Thanks,


in2sel : IN std_logic;

in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed;

In VHDL the operator > is an arithmetic comparison. This sort of
comparison is not defined for std_logic that I am aware of. If you mean
comparisons such as arithmetic > for std_logic_vector (which would be
"000" rather than '0') there are definitions of the > operation on this
data type.

You can assign the std_logic_vector to a signed or unsigned type defined
in the NUMERIC_STD library. This will let you do the arithmetic
comparison on the signed or unsigned value. Or you can use the new
VHDL-2008 standard arithmetic package, IEEE.Numeric_Std_Unsigned. I
have not used it myself, but I believe it defines unsigned arithmetic
for std_logic_vector types. I see some mention of a similar library,
IEEE.Numeric_Std_signed, but some pages say there is only the unsigned
library.

If you really want the std_logic type, you can convert the many values
of std_logic to a 1 or 0 using to_01(). Then you can just use the
equality comparison which *is* defined for std_logic as the returned
value will be either a 1 or a 0 always. But this still may not be what
you want if the input is a 'W', 'X', 'Z', '-' or 'U'.

You can also define your own comparison or conversion operators.

--

Rick

 

[Thomas Stanka]

Am Mittwoch, 21. Oktober 2015 04:38:57 UTC+2 schrieb fl:

> in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed;

Writing this line is for me a clear selfnomination for the "Kick-me-my-name-is-McFly" award of today.

In fact std_ulogic is an enumerated type and has of course a order defined by the order you write it in the type definition.

TYPE color IS (red, green, yellow); -- yellow>green>red

There is also an order within std_ulogic. But I think is is not '1' > 'H' > '0' > 'L' and therefore you might experience some strange effects when simulating that line above with std_ulogic.

 

[fl]

On Wednesday, October 21, 2015 at 4:54:58 AM UTC-4, Thomas Stanka wrote:

Am Mittwoch, 21. Oktober 2015 04:38:57 UTC+2 schrieb fl:

in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed;

Writing this line is for me a clear selfnomination for the "Kick-me-my-name-is-McFly" award of today.

In fact std_ulogic is an enumerated type and has of course a order defined by the order you write it in the type definition.

TYPE color IS (red, green, yellow); -- yellow>green>red

There is also an order within std_ulogic. But I think is is not '1' > 'H' > '0' > 'L' and therefore you might experience some strange effects when simulating that line above with std_ulogic.

The code in my original post is generated from Matlab. I rewrite it in a
simplest VHDL module using it with a test bench. There is no compiling error
either. This kind of module generally is inside of (called from) other
module. With your replies, the comparison is on the enumerated type of
std_logic, which is in the IEEE package. Can we think it has been determined
i.e. a consistent result will always be got?

Use to_01() should work, though a little extra code.

It should have a simple way for such a situation.

 

[KJ]

On Tuesday, October 20, 2015 at 10:38:57 PM UTC-4, fl wrote:

'in2sel' is the
entity input port. I am curious about ( in2sel > '0' ). I guess in2sel should
be resolved to '1' or '0' (Otherwise 'X' 'Z' 'H' etc. have some pre-determined
order/priorities). Assume in2sel is resolved to '1'. What does '1' > '0' mean?
i.e. the comparing is on what category? Is it an integer subtype? Or something
else? I don't find the solution after a web search. Hopefully someone gives
me an interpretation or hint.

Since insel is type std_logic and std_logic is an enumeration type, the interpretation of > or < is whether the value is to the left or to the right of the other value in the definition of the enumeration type list. The definition of std_ulogic is

type STD_ULOGIC is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);

Type std_logic is just the resolved subtype form of std_ulogic, so it will have the same values as std_ulogic. The ordering of the literals that make up the enumeration is from left to right so 'U' is to the left of 'X' (as an example). An enumeration is considered 'greater' if it is to the right of another so 'X' is considered to be greater than 'U' so the expression 'X' > 'U' returns the boolean value of True. Similarly, since '1' is to the right of '0', an expression that boils down to '1' > '0' would result in the boolean value of True. In your case, you have "insel > '0'", so the following values for insel will all be true: '1', 'Z', 'W', 'L', 'H', '-'.

There is no numeric interpretation of > or < going on here because the comparison is not between anything that has a numeric value. VHDL allows for enumeration types to be defined and there are good use cases for where you would like to evaluate to see if some signal is > or < some other signal or constant that is also the same enumeration type. The code generated by Matlab would likely not be considered one of those 'good' use cases but remember the Matlab program itself is a program, not a person. Probably a more clearly written way to express that line of code would be the following.

in2_im0 <= dmut_im WHEN ( in2sel = '1' ) ELSE dim_signed;

Here the = is used rather than > and now suddenly there should be no confusion and yet =, > and < are all very familiar comparison operators. The difference here is while it is easy to understand that = simply means the same, unless you what an enumeration type is, there may be confusion about > or <. But that confusion probably does not exist if you ask yourself to compare strings so that they can be sorted (i.e. "def" > "abc"). Here you're comparing strings and the 'greater' string would be sorted after the other one. Now consider that strings are simply arrays of characters and VHDL defines characters as an enumeration in package standard.

type CHARACTER is (
NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
BS, HT, LF, VT, FF, CR, SO, SI,
DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
... etc ...

Kevin Jennings

 

[rickman]

On 10/21/2015 6:27 AM, fl wrote:

On Wednesday, October 21, 2015 at 4:54:58 AM UTC-4, Thomas Stanka wrote:
Am Mittwoch, 21. Oktober 2015 04:38:57 UTC+2 schrieb fl:

in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed;

Writing this line is for me a clear selfnomination for the "Kick-me-my-name-is-McFly" award of today.

In fact std_ulogic is an enumerated type and has of course a order defined by the order you write it in the type definition.

TYPE color IS (red, green, yellow); -- yellow>green>red

There is also an order within std_ulogic. But I think is is not '1' > 'H' > '0' > 'L' and therefore you might experience some strange effects when simulating that line above with std_ulogic.

The code in my original post is generated from Matlab. I rewrite it in a
simplest VHDL module using it with a test bench. There is no compiling error
either. This kind of module generally is inside of (called from) other
module. With your replies, the comparison is on the enumerated type of
std_logic, which is in the IEEE package. Can we think it has been determined
i.e. a consistent result will always be got?

Use to_01() should work, though a little extra code.

It should have a simple way for such a situation.

If you are trying to work with synthesized code from Matlab, why do you
care about the contents as long as it works? Or are you just trying to
learn more about VHDL by studying this example (if a poor one).

Clearly the code in2sel > '0' will work if they never allow the value of
in2sel to be anything other than '1' or '0'. Even so, it is awkward
code. It should have just been ins2sel = '1' instead.

--

Rick

 

[Thomas Stanka]

Am Mittwoch, 21. Oktober 2015 12:27:20 UTC+2 schrieb fl:

On Wednesday, October 21, 2015 at 4:54:58 AM UTC-4, Thomas Stanka wrote:
in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed;

Writing this line is for me a clear selfnomination for the "Kick-me-my-name-is-McFly" award of today.

The code in my original post is generated from Matlab.

So kick it, its name is Matlab .

This code will most likely work well with some preconditions, but will not have the intended behavior when applying full range of std_logic => bad reuseability. Maybe Matlab will claim, that reuseability is not their business.

As Rickman and KJ allready pointed out, the code would be functional and far better readable with using "=" for single bit compare function.
On the plus side, you learned some new aspect of VHDL with this code line.

bye Thomas