Question about setting signal value

F

fl

Guest
Hi,

When I run a simulation VHDL code, there is a out of range fatal error. The
signal source is from below code. corner0 is 111.5 while DINar_corner is
111.9. The division result should be below 1. Now the console output is:
# ** Note: The value of 'corner0' is 1.119000e+002
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1
# ** Note: The value of 'DINar_corner' is 1.115000e+002
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1
# ** Note: The value of 'Cout' is -1.000000e+308
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1

I think that Cout should be the correct value after the process updates the
signal value. But the other module which accespts Cout of below code, still
sees Cout's value as -1.000000e+308. This results an out of range error.


What is wrong in my code and signal value understanding?


Thanks a lot to you.



..............
p1: process (clk)
variable tmp_XP, tmp_X : real;
begin
if (clk'event and clk = '1') then
if reset = '1' then
ar <= 0.0; ai <= 0.0;
br <= 0.0; bi <= 0.0;
else
if cnt < x"02" then
if cnt = x"00" then
corner0 <= DINar_corner;
elsif abs(corner0) < abs(DINar_corner) then
corner0_q_real <= corner0/DINar_corner;
Cout <= corner0_q_real;
report "The value of 'corner0' is " & real'image(corner0);
report "The value of 'DINar_corner' is " & real'image(DINar_corner);
report "The value of 'Cout' is " & real'image(corner0_q_real);
Sout <= 1;
else
corner0_q_real <= DINar_corner/corner0;
Cout <= corner0_q_real;
report "The value of 'Cout' is " & real'image(corner0_q_real);
Sout <= 0;
end if;
else
corner0_q_real <= DINar_corner/corner0;
end if;
 
On Tuesday, September 29, 2015 at 5:05:40 PM UTC-4, fl wrote:
Hi,

When I run a simulation VHDL code, there is a out of range fatal error. The
signal source is from below code. corner0 is 111.5 while DINar_corner is
111.9. The division result should be below 1. Now the console output is:
# ** Note: The value of 'corner0' is 1.119000e+002
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1
# ** Note: The value of 'DINar_corner' is 1.115000e+002
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1
# ** Note: The value of 'Cout' is -1.000000e+308
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1

I think that Cout should be the correct value after the process updates the
signal value. But the other module which accespts Cout of below code, still
sees Cout's value as -1.000000e+308. This results an out of range error.


What is wrong in my code and signal value understanding?


Thanks a lot to you.



.............
p1: process (clk)
variable tmp_XP, tmp_X : real;
begin
if (clk'event and clk = '1') then
if reset = '1' then
ar <= 0.0; ai <= 0.0;
br <= 0.0; bi <= 0.0;
else
if cnt < x"02" then
if cnt = x"00" then
corner0 <= DINar_corner;
elsif abs(corner0) < abs(DINar_corner) then
corner0_q_real <= corner0/DINar_corner;
Cout <= corner0_q_real;
report "The value of 'corner0' is " & real'image(corner0);
report "The value of 'DINar_corner' is " & real'image(DINar_corner);
report "The value of 'Cout' is " & real'image(corner0_q_real);
Sout <= 1;
else
corner0_q_real <= DINar_corner/corner0;
Cout <= corner0_q_real;
report "The value of 'Cout' is " & real'image(corner0_q_real);
Sout <= 0;
end if;
else
corner0_q_real <= DINar_corner/corner0;
end if;
Click to expand...

It is found that when I replace below one line to the two lines in previous
post, it has no fatal error any more. I originally added one temporary
signal for observation. It really delays one clock for the value. It was
bug.
Thanks,

Cout <= -DINar_corner/corner0;
 
On Tuesday, September 29, 2015 at 6:31:01 PM UTC-4, rickman wrote:
On 9/29/2015 5:44 PM, fl wrote:
On Tuesday, September 29, 2015 at 5:05:40 PM UTC-4, fl wrote:
Hi,

When I run a simulation VHDL code, there is a out of range fatal error. The
signal source is from below code. corner0 is 111.5 while DINar_corner is
111.9. The division result should be below 1. Now the console output is:
# ** Note: The value of 'corner0' is 1.119000e+002
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1
# ** Note: The value of 'DINar_corner' is 1.115000e+002
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1
# ** Note: The value of 'Cout' is -1.000000e+308
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1

I think that Cout should be the correct value after the process updates the
signal value. But the other module which accespts Cout of below code, still
sees Cout's value as -1.000000e+308. This results an out of range error.


What is wrong in my code and signal value understanding?


Thanks a lot to you.



.............
p1: process (clk)
variable tmp_XP, tmp_X : real;
begin
if (clk'event and clk = '1') then
if reset = '1' then
ar <= 0.0; ai <= 0.0;
br <= 0.0; bi <= 0.0;
else
if cnt < x"02" then
if cnt = x"00" then
corner0 <= DINar_corner;
elsif abs(corner0) < abs(DINar_corner) then
corner0_q_real <= corner0/DINar_corner;
Cout <= corner0_q_real;
report "The value of 'corner0' is " & real'image(corner0);
report "The value of 'DINar_corner' is " & real'image(DINar_corner);
report "The value of 'Cout' is " & real'image(corner0_q_real);
Sout <= 1;
else
corner0_q_real <= DINar_corner/corner0;
Cout <= corner0_q_real;
report "The value of 'Cout' is " & real'image(corner0_q_real);
Sout <= 0;
end if;
else
corner0_q_real <= DINar_corner/corner0;
end if;

It is found that when I replace below one line to the two lines in previous
post, it has no fatal error any more. I originally added one temporary
signal for observation. It really delays one clock for the value. It was
bug.
Thanks,

Cout <= -DINar_corner/corner0;

Yes, this statement inside the clocked conditional results in a 1 clock
cycle delay, or actually more since it is in the ELSE clause while the
rest of the code is in the THEN part of the IF cnt < x"02" statement.

I think it would work fine if you made the
Cout <= -DINar_corner/corner0;
statement a concurrent statement outside of the process. Then it will
be updated as soon as the values of DINar_corner and corner0 are updated.

--

Rick
Click to expand...

Thanks. But there is another reciprocal case at the 'if' clause:

corner0_q_real <= corner0/DINar_corner;

which are conditioned on the two data absolute value (ABS) comparison.
 
On 9/29/2015 5:44 PM, fl wrote:
On Tuesday, September 29, 2015 at 5:05:40 PM UTC-4, fl wrote:
Hi,

When I run a simulation VHDL code, there is a out of range fatal error. The
signal source is from below code. corner0 is 111.5 while DINar_corner is
111.9. The division result should be below 1. Now the console output is:
# ** Note: The value of 'corner0' is 1.119000e+002
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1
# ** Note: The value of 'DINar_corner' is 1.115000e+002
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1
# ** Note: The value of 'Cout' is -1.000000e+308
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1

I think that Cout should be the correct value after the process updates the
signal value. But the other module which accespts Cout of below code, still
sees Cout's value as -1.000000e+308. This results an out of range error.


What is wrong in my code and signal value understanding?


Thanks a lot to you.



.............
p1: process (clk)
variable tmp_XP, tmp_X : real;
begin
if (clk'event and clk = '1') then
if reset = '1' then
ar <= 0.0; ai <= 0.0;
br <= 0.0; bi <= 0.0;
else
if cnt < x"02" then
if cnt = x"00" then
corner0 <= DINar_corner;
elsif abs(corner0) < abs(DINar_corner) then
corner0_q_real <= corner0/DINar_corner;
Cout <= corner0_q_real;
report "The value of 'corner0' is " & real'image(corner0);
report "The value of 'DINar_corner' is " & real'image(DINar_corner);
report "The value of 'Cout' is " & real'image(corner0_q_real);
Sout <= 1;
else
corner0_q_real <= DINar_corner/corner0;
Cout <= corner0_q_real;
report "The value of 'Cout' is " & real'image(corner0_q_real);
Sout <= 0;
end if;
else
corner0_q_real <= DINar_corner/corner0;
end if;

It is found that when I replace below one line to the two lines in previous
post, it has no fatal error any more. I originally added one temporary
signal for observation. It really delays one clock for the value. It was
bug.
Thanks,

Cout <= -DINar_corner/corner0;
Click to expand...

Yes, this statement inside the clocked conditional results in a 1 clock
cycle delay, or actually more since it is in the ELSE clause while the
rest of the code is in the THEN part of the IF cnt < x"02" statement.

I think it would work fine if you made the
Cout <= -DINar_corner/corner0;
statement a concurrent statement outside of the process. Then it will
be updated as soon as the values of DINar_corner and corner0 are updated.

--

Rick
 
On 9/29/2015 8:13 PM, fl wrote:
On Tuesday, September 29, 2015 at 6:31:01 PM UTC-4, rickman wrote:
On 9/29/2015 5:44 PM, fl wrote:
On Tuesday, September 29, 2015 at 5:05:40 PM UTC-4, fl wrote:
Hi,

When I run a simulation VHDL code, there is a out of range fatal error. The
signal source is from below code. corner0 is 111.5 while DINar_corner is
111.9. The division result should be below 1. Now the console output is:
# ** Note: The value of 'corner0' is 1.119000e+002
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1
# ** Note: The value of 'DINar_corner' is 1.115000e+002
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1
# ** Note: The value of 'Cout' is -1.000000e+308
# Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1

I think that Cout should be the correct value after the process updates the
signal value. But the other module which accespts Cout of below code, still
sees Cout's value as -1.000000e+308. This results an out of range error.


What is wrong in my code and signal value understanding?


Thanks a lot to you.



.............
p1: process (clk)
variable tmp_XP, tmp_X : real;
begin
if (clk'event and clk = '1') then
if reset = '1' then
ar <= 0.0; ai <= 0.0;
br <= 0.0; bi <= 0.0;
else
if cnt < x"02" then
if cnt = x"00" then
corner0 <= DINar_corner;
elsif abs(corner0) < abs(DINar_corner) then
corner0_q_real <= corner0/DINar_corner;
Cout <= corner0_q_real;
report "The value of 'corner0' is " & real'image(corner0);
report "The value of 'DINar_corner' is " & real'image(DINar_corner);
report "The value of 'Cout' is " & real'image(corner0_q_real);
Sout <= 1;
else
corner0_q_real <= DINar_corner/corner0;
Cout <= corner0_q_real;
report "The value of 'Cout' is " & real'image(corner0_q_real);
Sout <= 0;
end if;
else
corner0_q_real <= DINar_corner/corner0;
end if;

It is found that when I replace below one line to the two lines in previous
post, it has no fatal error any more. I originally added one temporary
signal for observation. It really delays one clock for the value. It was
bug.
Thanks,

Cout <= -DINar_corner/corner0;

Yes, this statement inside the clocked conditional results in a 1 clock
cycle delay, or actually more since it is in the ELSE clause while the
rest of the code is in the THEN part of the IF cnt < x"02" statement.

I think it would work fine if you made the
Cout <= -DINar_corner/corner0;
statement a concurrent statement outside of the process. Then it will
be updated as soon as the values of DINar_corner and corner0 are updated.

--

Rick

Thanks. But there is another reciprocal case at the 'if' clause:

corner0_q_real <= corner0/DINar_corner;

which are conditioned on the two data absolute value (ABS) comparison.
Click to expand...

Ok then make it a when clause

corner0_q_real <= corner0/DINar_corner
when abs(corner0) < abs(DINar_corner)
else DINar_corner/corner0;

Or you can have two signals with one used in each part of the IF statement.

The point is it needs to be combinatorial logic rather than sequential.

Another way of doing it is to use a variable, but it can't be used
outside the process unless you assign it to a signal and that largely
defeats the purpose of using it to monitor the value.

--

Rick
 
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