Guest
Hi, I have test next week and I've been playing with VHDL language recently and run into this error which I cant understand, maybe someone can help me..
I'm testing simple generator who generates numbers from 0 to 7. Here is the code :
-----------------------------------------------
package mxx is
subtype mytype is integer range 0 to 7;
end package;
library IEEE;
use WORK.mxx.ALL;
use IEEE.std_logic_1164.ALL;
entity eightval_generators is
generic (ti : time :=10 ns);
port (sk : out mytype);
end entity;
architecture normala of eightval_generators is
begin
process
begin
for i in 0 to 7 loop
sk <= i;
wait for ti;
end loop;
end process;
end architecture;
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I have created schematic for code with appropriate output port and my simulation type is TimeList Digital simulation. If I change mytype to integer I don't get error and all works. But for practice I wanted to use subtype and limit it to my needs and add all of this as package to my project. But this results in error which I would like to clear out .
I'm testing simple generator who generates numbers from 0 to 7. Here is the code :
-----------------------------------------------
package mxx is
subtype mytype is integer range 0 to 7;
end package;
library IEEE;
use WORK.mxx.ALL;
use IEEE.std_logic_1164.ALL;
entity eightval_generators is
generic (ti : time :=10 ns);
port (sk : out mytype);
end entity;
architecture normala of eightval_generators is
begin
process
begin
for i in 0 to 7 loop
sk <= i;
wait for ti;
end loop;
end process;
end architecture;
-----------------------------------------------
I have created schematic for code with appropriate output port and my simulation type is TimeList Digital simulation. If I change mytype to integer I don't get error and all works. But for practice I wanted to use subtype and limit it to my needs and add all of this as package to my project. But this results in error which I would like to clear out .