Quartus II Synthesis - System Memory Issues for Large Stratix 10 Design...

C

Chris Adams

Guest
Hello,

I have a Stratix 10 design that is based around an ip core generated using Intel\'s HLS. The core does some simple floating point operations and by itself uses very few resources (1 DSP, a few hundred flops etc).

This core sits inside a generate statement like this:

generate
for(i = 0; i < SOMEBIGNUMBER; i=i+1)
myhlscore u0 (inputs, outputs);
....


The design works and is proven in simulation and in hardware.

The problem comes when I try to increase the value of SOMEBIGNUMBER. Despite there being adequate resources, using values above 200 or so make the synthesis tool run out of memory.

I cannot alleviate this easily by adding more memory - I already tried synthesizing on a computer with 256GB memory and a 200GB swap space and quartus ate it all up before dying.

I\'m using a .ip file from HLS right now. I\'m wondering is there is some way to pre-synthesis the module and keep the results, or is there someway I need to write the generate statement so that it caches less? Perhaps there are some synthesis settings I can change?

Thanks,
C
 

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