PWM Amp Design

Genome · Apr 12, 2005

"Chris Carlen" <crcarleRemoveThis@BOGUSsandia.gov> wrote in message
news:d36fkj022dd@news3.newsguy.com...

Greetings:

Hello there.

Thanks for your comments.

Good day!

--
_______________________________________________________________________
Christopher R. Carlen

Try this one on for size...... OK, it's fiddled about with and it's current
mode control but it does something.

You'll need to join and then go to the Files section of

http://groups.yahoo.com/group/LTspice/

For the CMOS library and place it in the directory shown somewhere below.

Watch out for unintended line wrap.

I wouldn't claim it's 100% but, if it floats your boat, then I can put a few
words to it.

Version 4
SHEET 1 2256 1332
WIRE -272 576 -272 0
WIRE -272 688 -272 656
WIRE -272 704 -272 688
WIRE -272 1104 -272 832
WIRE -272 1216 -272 1184
WIRE -272 1248 -272 1216
WIRE -112 1072 -144 1072
WIRE -112 1104 -112 1072
WIRE -112 1216 -272 1216
WIRE -112 1216 -112 1184
WIRE -80 1024 -144 1024
WIRE -80 1072 -112 1072
WIRE -32 480 -32 96
WIRE -32 688 -272 688
WIRE -32 688 -32 480
WIRE -32 832 -272 832
WIRE -32 864 -32 832
WIRE -32 976 -32 944
WIRE -32 1008 -32 976
WIRE -32 1216 -112 1216
WIRE -32 1216 -32 1088
WIRE 0 48 -64 48
WIRE 0 96 -32 96
WIRE 0 432 -64 432
WIRE 0 480 -32 480
WIRE 0 832 -32 832
WIRE 48 0 -272 0
WIRE 48 32 48 0
WIRE 48 128 48 112
WIRE 48 240 -64 240
WIRE 48 240 48 128
WIRE 48 272 48 240
WIRE 48 400 48 272
WIRE 48 416 48 400
WIRE 48 512 48 496
WIRE 48 544 -64 544
WIRE 48 544 48 512
WIRE 48 576 48 544
WIRE 48 688 -32 688
WIRE 48 688 48 656
WIRE 64 976 -32 976
WIRE 64 1056 64 976
WIRE 80 272 48 272
WIRE 80 976 64 976
WIRE 160 0 48 0
WIRE 160 48 160 0
WIRE 160 128 48 128
WIRE 160 128 160 112
WIRE 160 400 48 400
WIRE 160 432 160 400
WIRE 160 512 48 512
WIRE 160 512 160 496
WIRE 192 176 -64 176
WIRE 192 272 160 272
WIRE 192 272 192 176
WIRE 208 976 192 976
WIRE 208 976 208 832
WIRE 224 976 208 976
WIRE 288 272 192 272
WIRE 336 176 192 176
WIRE 352 976 336 976
WIRE 352 976 352 896
WIRE 368 976 352 976
WIRE 400 272 368 272
WIRE 512 832 208 832
WIRE 512 976 480 976
WIRE 576 176 400 176
WIRE 576 272 480 272
WIRE 576 272 576 176
WIRE 592 0 160 0
WIRE 592 48 592 0
WIRE 592 128 592 112
WIRE 592 432 592 400
WIRE 592 512 592 496
WIRE 608 272 576 272
WIRE 640 976 624 976
WIRE 640 1024 640 976
WIRE 656 1024 640 1024
WIRE 656 1056 64 1056
WIRE 720 0 592 0
WIRE 720 32 720 0
WIRE 720 128 592 128
WIRE 720 128 720 112
WIRE 720 240 720 128
WIRE 720 272 688 272
WIRE 720 272 720 240
WIRE 720 400 592 400
WIRE 720 400 720 272
WIRE 720 416 720 400
WIRE 720 512 592 512
WIRE 720 512 720 496
WIRE 720 544 720 512
WIRE 720 576 720 544
WIRE 720 688 48 688
WIRE 720 688 720 656
WIRE 784 1040 768 1040
WIRE 800 96 768 96
WIRE 800 480 768 480
WIRE 800 480 800 96
WIRE 800 688 720 688
WIRE 800 688 800 480
WIRE 832 0 720 0
WIRE 832 48 768 48
WIRE 832 176 576 176
WIRE 832 240 720 240
WIRE 832 432 768 432
WIRE 832 544 720 544
WIRE 928 896 352 896
WIRE 928 1008 928 896
WIRE 928 1040 896 1040
WIRE 928 1120 928 1040
WIRE 960 1040 928 1040
WIRE 960 1040 960 864
WIRE 992 832 624 832
WIRE 992 864 960 864
WIRE 992 1008 928 1008
WIRE 992 1040 960 1040
WIRE 1120 0 1088 0
WIRE 1120 176 1088 176
WIRE 1120 432 1088 432
WIRE 1120 544 1088 544
WIRE 1136 848 1104 848
WIRE 1136 1024 1104 1024
WIRE 1136 1120 928 1120
WIRE 1232 0 1200 0
WIRE 1232 80 1232 0
WIRE 1232 176 1200 176
WIRE 1232 176 1232 80
WIRE 1232 320 1232 208
WIRE 1232 352 1232 320
WIRE 1232 432 1200 432
WIRE 1232 512 1232 432
WIRE 1232 544 1200 544
WIRE 1232 576 1232 544
WIRE 1232 688 800 688
WIRE 1232 688 1232 656
WIRE 1264 0 1232 0
WIRE 1264 80 1232 80
WIRE 1264 176 1232 176
WIRE 1264 208 1232 208
WIRE 1264 432 1232 432
WIRE 1264 512 1232 512
WIRE 1264 544 1232 544
WIRE 1376 0 1344 0
WIRE 1376 80 1328 80
WIRE 1376 432 1344 432
WIRE 1376 528 1328 528
WIRE 1376 528 1376 432
WIRE 1408 432 1376 432
WIRE 1472 0 1440 0
WIRE 1472 80 1440 80
WIRE 1472 80 1472 0
WIRE 1472 192 1328 192
WIRE 1472 192 1472 80
WIRE 1504 0 1472 0
WIRE 1712 176 1680 176
WIRE 1712 208 1712 176
WIRE 1712 320 1232 320
WIRE 1712 320 1712 288
WIRE 1728 432 1696 432
WIRE 1728 544 1696 544
WIRE 1744 0 1680 0
WIRE 1744 176 1712 176
WIRE 1840 432 1808 432
WIRE 1840 512 1840 432
WIRE 1840 544 1808 544
WIRE 1840 576 1840 544
WIRE 1840 688 1232 688
WIRE 1840 688 1840 656
WIRE 1856 0 1824 0
WIRE 1856 80 1856 0
WIRE 1856 176 1824 176
WIRE 1856 176 1856 80
WIRE 1856 320 1712 320
WIRE 1856 320 1856 208
WIRE 1872 432 1840 432
WIRE 1872 512 1840 512
WIRE 1872 544 1840 544
WIRE 1888 0 1856 0
WIRE 1888 80 1856 80
WIRE 1888 176 1856 176
WIRE 1888 208 1856 208
WIRE 1984 432 1952 432
WIRE 1984 528 1936 528
WIRE 1984 528 1984 432
WIRE 2000 0 1968 0
WIRE 2000 80 1952 80
WIRE 2016 432 1984 432
WIRE 2096 0 2064 0
WIRE 2096 80 2064 80
WIRE 2096 80 2096 0
WIRE 2096 192 1952 192
WIRE 2096 192 2096 80
WIRE 2128 0 2096 0
FLAG -64 48 PHA
IOPIN -64 48 In
FLAG 832 48 PHB
IOPIN 832 48 In
FLAG -64 432 PHB
IOPIN -64 432 In
FLAG 832 432 PHA
IOPIN 832 432 In
FLAG -272 704 0
FLAG -64 240 PREA
IOPIN -64 240 Out
FLAG 832 240 PREB
IOPIN 832 240 Out
FLAG -64 176 POSTA
IOPIN -64 176 Out
FLAG 832 176 POSTB
IOPIN 832 176 Out
FLAG -64 544 ISNSA
IOPIN -64 544 Out
FLAG 832 544 ISNSB
IOPIN 832 544 Out
FLAG 1136 1120 DEAD
IOPIN 1136 1120 Out
FLAG -144 1072 VTRI
IOPIN -144 1072 Out
FLAG -272 1248 0
FLAG 0 832 +15
IOPIN 0 832 Out
FLAG 1136 848 PHA
IOPIN 1136 848 Out
FLAG 1136 1024 PHB
IOPIN 1136 1024 Out
FLAG -144 1024 IERR
IOPIN -144 1024 In
FLAG 1088 432 ISNSA
IOPIN 1088 432 In
FLAG 1088 544 ISNSB
IOPIN 1088 544 In
FLAG 1408 432 ISNS
IOPIN 1408 432 Out
FLAG 1088 0 ISNS
IOPIN 1088 0 In
FLAG 1504 0 IERR
IOPIN 1504 0 Out
FLAG 1232 352 0
FLAG 832 0 VBUS
IOPIN 832 0 Out
FLAG 1696 432 POSTA
IOPIN 1696 432 In
FLAG 1696 544 POSTB
IOPIN 1696 544 In
FLAG 2016 432 VFB
IOPIN 2016 432 Out
FLAG 1680 0 VFB
IOPIN 1680 0 In
FLAG 2128 0 IDEM
IOPIN 2128 0 Out
FLAG 1088 176 IDEM
IOPIN 1088 176 In
FLAG 1680 176 VDEM
IOPIN 1680 176 Out
SYMBOL sw 48 128 M180
WINDOW 0 40 65 Left 0
WINDOW 3 38 41 Left 0
SYMATTR InstName S1
SYMATTR Value MSW
SYMBOL sw 720 128 R180
WINDOW 0 72 65 Left 0
WINDOW 3 44 40 Left 0
SYMATTR InstName S2
SYMATTR Value MSW
SYMBOL sw 48 512 M180
WINDOW 0 41 67 Left 0
WINDOW 3 40 43 Left 0
SYMATTR InstName S3
SYMATTR Value MSW
SYMBOL sw 720 512 R180
WINDOW 0 78 68 Left 0
WINDOW 3 51 44 Left 0
SYMATTR InstName S4
SYMATTR Value MSW
SYMBOL ind 64 288 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
SYMATTR InstName LFILTA
SYMATTR Value 25ľ
SYMBOL ind 592 288 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
SYMATTR InstName LFILTB
SYMATTR Value 25ľ
SYMBOL cap 400 160 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName CFILT
SYMATTR Value 4ľ7
SYMBOL res 384 256 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName RLOAD
SYMATTR Value 2R5
SYMBOL voltage -272 560 R0
WINDOW 0 37 43 Left 0
WINDOW 3 37 69 Left 0
SYMATTR InstName VBUS
SYMATTR Value 80V
SYMBOL diode 176 112 R180
WINDOW 0 -36 49 Left 0
WINDOW 3 -44 27 Left 0
SYMATTR InstName D1
SYMATTR Value DID
SYMBOL diode 608 112 R180
WINDOW 0 49 49 Left 0
WINDOW 3 39 25 Left 0
SYMATTR InstName D2
SYMATTR Value DID
SYMBOL diode 608 496 R180
WINDOW 0 44 53 Left 0
WINDOW 3 35 30 Left 0
SYMATTR InstName D4
SYMATTR Value DID
SYMBOL diode 176 496 R180
WINDOW 0 -36 50 Left 0
WINDOW 3 -48 29 Left 0
SYMATTR InstName D3
SYMATTR Value DID
SYMBOL res 704 560 R0
WINDOW 0 -62 40 Left 0
WINDOW 3 -64 65 Left 0
SYMATTR InstName R2
SYMATTR Value 0R1
SYMBOL res 32 560 R0
SYMATTR InstName R1
SYMATTR Value 0R1
SYMBOL Digital\\CD4000\\CD4070B 704 976 R0
WINDOW 0 -25 -8 Left 0
WINDOW 3 -27 14 Left 0
SYMATTR InstName U1
SYMATTR SpiceLine VDD=15 SPEED=1.0 TRIPDT=5e-9
SYMBOL Digital\\CD4000\\CD4050B 128 912 R0
SYMATTR InstName U2
SYMATTR SpiceLine VDD=15 SPEED=1.0 TRIPDT=5e-9
SYMBOL Digital\\CD4000\\CD4050B 272 912 R0
SYMATTR InstName U3
SYMATTR SpiceLine VDD=15 SPEED=1.0 TRIPDT=5e-9
SYMBOL Digital\\CD4000\\CD4050B 416 912 R0
SYMATTR InstName U4
SYMATTR SpiceLine VDD=15 SPEED=1.0 TRIPDT=5e-9
SYMBOL Digital\\CD4000\\CD4050B 560 912 R0
SYMATTR InstName U5
SYMATTR SpiceLine VDD=15 SPEED=1.0 TRIPDT=5e-9
SYMBOL sw -32 1104 M180
WINDOW 0 -105 141 Left 0
WINDOW 3 -106 115 Left 0
SYMATTR InstName S5
SYMATTR Value COMP
SYMBOL res -48 848 R0
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL voltage -112 1088 R0
WINDOW 0 -93 58 Left 0
WINDOW 3 24 104 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VTRI
SYMATTR Value PULSE(-1 1 0 4u 4u 0 8u)
SYMBOL voltage -272 1088 R0
WINDOW 0 -90 46 Left 0
WINDOW 3 -89 70 Left 0
SYMATTR InstName VDD
SYMATTR Value 15V
SYMBOL Digital\\CD4000\\CD4049B 560 768 R0
SYMATTR InstName U6
SYMATTR SpiceLine VDD=15 SPEED=1.0 TRIPDT=5e-9
SYMBOL Digital\\CD4000\\CD4049B 832 976 R0
SYMATTR InstName U7
SYMATTR SpiceLine VDD=15 SPEED=1.0 TRIPDT=5e-9
SYMBOL Digital\\CD4000\\CD4081B 1040 784 R0
SYMATTR InstName U8
SYMATTR SpiceLine VDD=15 SPEED=1.0 TRIPDT=5e-9
SYMBOL Digital\\CD4000\\CD4081B 1040 960 R0
SYMATTR InstName U9
SYMATTR SpiceLine VDD=15 SPEED=1.0 TRIPDT=5e-9
SYMBOL ind 384 288 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 1 56 VBottom 0
SYMATTR InstName LLOAD
SYMATTR Value 250ľ
SYMBOL Opamps\\opamp 1296 464 R0
SYMATTR InstName U10
SYMBOL res 1216 416 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R6
SYMATTR Value 10K
SYMBOL res 1360 416 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R7
SYMATTR Value 10K
SYMBOL res 1216 528 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R8
SYMATTR Value 10K
SYMBOL res 1216 560 R0
SYMATTR InstName R9
SYMATTR Value 10K
SYMBOL Opamps\\opamp 1296 128 R0
SYMATTR InstName U11
SYMBOL res 1216 -16 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R10
SYMATTR Value 10K
SYMBOL res 1360 -16 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R11
SYMATTR Value 15K
SYMBOL cap 1440 -16 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL res 1216 160 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R12
SYMATTR Value 10K
SYMBOL diode 1264 96 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D5
SYMATTR Value ZID
SYMBOL diode 1440 64 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName D6
SYMATTR Value ZID
SYMBOL Opamps\\opamp 1904 464 R0
SYMATTR InstName U12
SYMBOL res 1824 416 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R4
SYMATTR Value 1E6
SYMBOL res 1968 416 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL res 1824 528 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R13
SYMATTR Value 1E6
SYMBOL res 1824 560 R0
SYMATTR InstName R14
SYMATTR Value 10K
SYMBOL Opamps\\opamp 1920 128 R0
SYMATTR InstName U13
SYMBOL res 1840 -16 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R15
SYMATTR Value 10K
SYMBOL res 1984 -16 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R16
SYMATTR Value 62K
SYMBOL cap 2064 -16 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C2
SYMATTR Value 330p
SYMBOL res 1840 160 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R17
SYMATTR Value 10K
SYMBOL voltage 1712 192 R0
WINDOW 0 -104 54 Left 0
WINDOW 3 -104 72 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDEM
SYMATTR Value PULSE(0 0.4 50u 10n 10n 1m 1m)
SYMBOL diode 1888 96 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D7
SYMATTR Value ZID
SYMBOL diode 2064 64 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName D8
SYMATTR Value ZID
TEXT -280 744 Left 0 !.MODEL MSW SW(RON=10m ROFF=1E6 VT=5V VH=-2V)
TEXT -280 768 Left 0 !.MODEL DID D(RON=10m)
TEXT 24 1200 Left 0 !.tran 0 200u 1u uic
TEXT 24 1176 Left 0 !.include C:\\Program
Files\\LTC\\SwCADIII\\lib\\cmp\\Cd4000.lib
TEXT 24 1128 Left 0 !.MODEL COMP SW(RON=10m ROFF=1E6 VT=0 VH=1m)
TEXT 24 1152 Left 0 !.lib opamp.sub
TEXT -280 792 Left 0 !.MODEL ZID D(RON=10m VREV=2)

DNA

Fuck off Barry

Chris Carlen · Apr 12, 2005

Genome wrote:

Try this one on for size...... OK, it's fiddled about with and it's current
mode control but it does something.

You'll need to join and then go to the Files section of

http://groups.yahoo.com/group/LTspice/

For the CMOS library and place it in the directory shown somewhere below.

Watch out for unintended line wrap.

I wouldn't claim it's 100% but, if it floats your boat, then I can put a few
words to it.

Ok, I got it running after a few fixes. Something strange happens when
you Europeans post these things. I had something looking like an
Angstrom symbol before the "u" characters in the inductors. Also, you
had the VDEM pulse source set to Ton=1m and the Period=1m, as well as
the sim time only 200u which didn't make for a very interesting first run.

Ok, so now I see a circuit from which I can definitely learn some things
even if I don't use it right away. It is from scratch, so I'd have to
build up the FET drivers. HIP4080 would do, but that's a lot of work
when I've got a working but crude SA60 circuit ready to go.

I like the current limiting. Well it's really more than that, since
it's current mode.

The only trouble is that I get considerable overshoot, about 40% on the
upswing, and then a long settling time. The swing back to zero rings
quite a bit. It is interesting how the step response is affected by
where the step is attempting to go. I have been observing these effects
for a while in my own circuit.

Perhaps I can use the PWM generator with dead time generation in the
future. That is pretty cool.

Here is what I am working with and planning to implement. It's
controller arrangement is basically right out of the Apex App note 33,
but the H-bridge is my concoction. I should try different implentations
of SPICEd PWM generation, as I'm not certain the B source comparator
provides the quickest sim times.

I'm presently attempting to figure out what frequency response to set
the voltage sense amp to. I have discovered that if the amp slew rate
limits, then the DC gain accuracy is bungled. Other than that, too slow
of a sense amp is also not good.

Another peculiar phenomenon is that at certain frequency response
settings of the sense amp, the voltage sense ripple interacts with the
PWM ramp to skip every other cycle, causing the output ripple to go way
up. Strange. Hopefully you will see that happen with the settings I'm
providing here:

---------------------------------------------------------------
Version 4
SHEET 1 1964 820
WIRE -1168 -144 -1248 -144
WIRE -1168 96 -1248 96
WIRE -1040 -144 -1088 -144
WIRE -1040 -112 -1040 -144
WIRE -1040 0 -1040 -32
WIRE -1040 96 -1088 96
WIRE -1040 128 -1040 96
WIRE -1040 240 -1040 208
WIRE -928 -144 -1040 -144
WIRE -928 -112 -928 -144
WIRE -928 0 -1040 0
WIRE -928 0 -928 -48
WIRE -928 16 -928 0
WIRE -928 96 -1040 96
WIRE -928 128 -928 96
WIRE -928 240 -1040 240
WIRE -928 240 -928 192
WIRE -928 256 -928 240
WIRE -864 -144 -928 -144
WIRE -864 96 -928 96
WIRE -752 96 -784 96
WIRE -752 144 -752 96
WIRE -752 256 -752 224
WIRE -720 -144 -784 -144
WIRE -720 -48 -720 -144
WIRE -720 64 -720 -48
WIRE -688 -48 -720 -48
WIRE -672 -144 -720 -144
WIRE -672 64 -720 64
WIRE -672 96 -752 96
WIRE -640 48 -640 16
WIRE -640 144 -640 112
WIRE -624 16 -640 16
WIRE -624 144 -640 144
WIRE -560 -144 -608 -144
WIRE -560 -48 -608 -48
WIRE -560 -48 -560 -144
WIRE -560 80 -608 80
WIRE -560 80 -560 -48
WIRE -528 -144 -560 -144
WIRE -400 192 -432 192
WIRE -400 304 -400 192
WIRE -400 416 -400 384
WIRE -384 80 -560 80
WIRE -368 192 -400 192
WIRE -288 80 -304 80
WIRE -288 80 -288 64
WIRE -208 64 -288 64
WIRE -208 80 -208 64
WIRE -208 192 -288 192
WIRE -208 192 -208 80
WIRE -176 256 -176 224
WIRE -144 -320 -144 -368
WIRE -144 -208 -144 -240
WIRE -144 80 -208 80
WIRE -144 192 -208 192
WIRE -144 224 -176 224
WIRE -112 176 -112 144
WIRE -112 272 -112 240
WIRE -96 144 -112 144
WIRE -96 272 -112 272
WIRE -16 -320 -16 -368
WIRE -16 -208 -16 -240
WIRE 16 80 -80 80
WIRE 16 208 -80 208
WIRE 16 208 16 80
WIRE 16 304 16 256
WIRE 16 416 16 384
WIRE 128 -320 128 -368
WIRE 128 -208 128 -240
WIRE 144 -368 128 -368
WIRE 208 208 16 208
WIRE 208 208 208 160
WIRE 208 256 16 256
WIRE 208 304 208 256
WIRE 224 160 208 160
WIRE 224 304 208 304
WIRE 368 208 208 208
WIRE 368 256 208 256
WIRE 400 -192 400 -368
WIRE 400 128 400 -192
WIRE 400 192 400 128
WIRE 400 336 400 272
WIRE 512 -112 512 -144
WIRE 512 80 512 48
WIRE 528 -192 400 -192
WIRE 528 -144 512 -144
WIRE 528 80 512 80
WIRE 528 128 400 128
WIRE 576 -208 576 -304
WIRE 576 -48 544 -48
WIRE 576 -48 576 -128
WIRE 576 64 576 -48
WIRE 576 192 576 144
WIRE 576 304 576 272
WIRE 576 336 576 304
WIRE 688 -48 576 -48
WIRE 688 0 688 -48
WIRE 688 128 688 80
WIRE 688 304 576 304
WIRE 688 304 688 192
WIRE 720 -48 688 -48
WIRE 832 -144 832 -192
WIRE 832 -48 800 -48
WIRE 832 -48 832 -144
WIRE 832 64 832 -48
WIRE 832 304 688 304
WIRE 832 304 832 128
WIRE 880 -144 832 -144
WIRE 880 -48 832 -48
WIRE 1008 -144 960 -144
WIRE 1008 -48 960 -48
WIRE 1136 -144 1072 -144
WIRE 1136 -144 1136 -192
WIRE 1136 -48 1088 -48
WIRE 1136 -48 1136 -144
WIRE 1136 64 1136 -48
WIRE 1136 304 832 304
WIRE 1136 304 1136 128
WIRE 1168 -48 1136 -48
WIRE 1280 -48 1248 -48
WIRE 1280 0 1280 -48
WIRE 1280 128 1280 80
WIRE 1280 304 1136 304
WIRE 1280 304 1280 192
WIRE 1392 -304 576 -304
WIRE 1392 -208 1392 -304
WIRE 1392 -48 1280 -48
WIRE 1392 -48 1392 -128
WIRE 1392 64 1392 -48
WIRE 1392 192 1392 144
WIRE 1392 304 1280 304
WIRE 1392 304 1392 272
WIRE 1424 -48 1392 -48
WIRE 1456 -144 1440 -144
WIRE 1456 -112 1456 -144
WIRE 1456 80 1440 80
WIRE 1456 80 1456 48
WIRE 1520 -368 400 -368
WIRE 1520 -192 1440 -192
WIRE 1520 -192 1520 -368
WIRE 1520 128 1440 128
WIRE 1520 128 1520 -192
WIRE 1616 -304 1392 -304
WIRE 1616 -304 1616 -336
WIRE 1616 -128 1616 -304
WIRE 1616 32 1616 -48
WIRE 1616 304 1392 304
WIRE 1616 304 1616 96
WIRE 1728 304 1616 304
WIRE 1728 336 1728 304
WIRE 1760 -64 1760 -144
WIRE 1760 96 1760 0
WIRE 1872 -304 1616 -304
WIRE 1872 -272 1872 -304
WIRE 1872 -144 1760 -144
WIRE 1872 -144 1872 -192
WIRE 1872 -64 1872 -144
WIRE 1872 96 1760 96
WIRE 1872 96 1872 16
WIRE 1872 304 1728 304
WIRE 1872 304 1872 96
FLAG 16 416 0
FLAG -144 -208 0
FLAG -16 -208 0
FLAG -144 -368 Vpos
FLAG -16 -368 Vneg
FLAG 224 304 C_neg
FLAG 224 160 C_pos
FLAG 576 336 0
FLAG 1728 336 0
FLAG 400 336 0
FLAG -400 416 0
FLAG -96 144 Vpos
FLAG -96 272 Vneg
FLAG 512 -112 0
FLAG 1456 48 0
FLAG 512 48 0
FLAG 1456 -112 0
FLAG 544 -48 Vo_p
FLAG 1424 -48 Vo_n
FLAG 832 -192 Vop
FLAG 1136 -192 Von
FLAG -176 256 0
FLAG -624 16 Vpos
FLAG -624 144 Vneg
FLAG -752 256 0
FLAG -928 256 0
FLAG -928 16 0
FLAG -1248 96 Vo_p
FLAG -1248 -144 Vo_n
FLAG -432 192 Vref
FLAG -528 -144 Vdiff
FLAG 128 -208 0
FLAG 144 -368 Vdelay
FLAG 1616 -336 Vs
SYMBOL voltage 16 288 R0
WINDOW 3 -110 185 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 42 60 Left 0
SYMATTR Value PULSE(5 10 0 4u 4u 1n 8u)
SYMATTR InstName Vramp
SYMBOL voltage -144 -336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL voltage -16 -224 R180
WINDOW 0 24 104 Left 0
WINDOW 3 24 16 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 15
SYMBOL bv 400 176 R0
WINDOW 3 -107 214 Left 0
WINDOW 0 46 55 Left 0
SYMATTR Value V=if( v(Vdelay), limit( {Cgain}*(v(C_pos)-v(C_neg)), -1, 1
), 0 )
SYMATTR InstName B1
SYMBOL cap 1600 32 R0
SYMATTR InstName C3
SYMATTR Value 1000
SYMBOL current 1872 16 R180
WINDOW 0 24 88 Left 0
WINDOW 3 24 0 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value 10
SYMBOL zener 1776 0 R180
WINDOW 0 24 72 Left 0
WINDOW 3 -19 -121 Left 0
SYMATTR InstName D3
SYMATTR Value ZD1
SYMBOL res 1856 -288 R0
SYMATTR InstName R7
SYMATTR Value 0.02
SYMBOL res 1600 -144 R0
SYMATTR InstName R8
SYMATTR Value 0.03
SYMBOL res 560 176 R0
SYMATTR InstName R9
SYMATTR Value 0.001
SYMBOL res 1376 176 R0
SYMATTR InstName R10
SYMATTR Value 0.001
SYMBOL Opamps\\2pole -112 208 R0
SYMATTR InstName U1
SYMATTR Value2 Avol=100k GBW=10Meg Slew=10Meg
SYMBOL voltage -400 288 R0
WINDOW 3 -98 195 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
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SYMBOL sw 576 -112 M180
SYMATTR InstName S1
SYMBOL sw 1392 -224 M0
SYMATTR InstName S2
SYMBOL sw 1392 48 M0
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SYMBOL sw 576 160 M180
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WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
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SYMATTR Value 22.5
SYMBOL ind 1152 -32 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
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SYMATTR Value 22.5
SYMBOL cap 816 64 R0
SYMATTR InstName C1
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SYMBOL cap 1120 64 R0
SYMATTR InstName C2
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SYMBOL ind 992 -32 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
SYMATTR InstName L3
SYMATTR Value 250
SYMBOL res 864 -32 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 2.5
SYMBOL res -400 96 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res -384 208 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL Opamps\\2pole -640 80 R0
SYMATTR InstName U2
SYMATTR Value2 Avol=100k GBW=30Meg Slew=100Meg
SYMBOL res -704 -32 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R4
SYMATTR Value {Rdiff}
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WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R5
SYMATTR Value {Rdiff}
SYMBOL res -880 112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R6
SYMATTR Value {Rdiff}
SYMBOL res -768 128 R0
SYMATTR InstName R11
SYMATTR Value {Rdiff}
SYMBOL cap -672 -128 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C5
SYMATTR Value {C2diff}
SYMBOL cap -944 -112 R0
SYMATTR InstName C6
SYMATTR Value {C1diff}
SYMBOL cap -944 128 R0
SYMATTR InstName C7
SYMATTR Value {C1diff}
SYMBOL res -1184 -128 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R12
SYMATTR Value {Rdiv1}
SYMBOL res -1184 112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R13
SYMATTR Value {Rdiv1}
SYMBOL res -1056 -128 R0
SYMATTR InstName R14
SYMATTR Value {Rdiv2}
SYMBOL res -1056 112 R0
SYMATTR InstName R15
SYMATTR Value {Rdiv2}
SYMBOL voltage 128 -336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 500n 5n)
SYMBOL cap -144 96 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C4
SYMATTR Value 820p
SYMBOL res 864 -128 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R23
SYMATTR Value 2.5
SYMBOL cap 1008 -128 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C9
SYMATTR Value 40
SYMBOL res 672 -16 R0
SYMATTR InstName R16
SYMATTR Value 1
SYMBOL res 1264 -16 R0
SYMATTR InstName R17
SYMATTR Value 1
SYMBOL cap 672 128 R0
SYMATTR InstName C8
SYMATTR Value 100p
SYMBOL cap 1264 128 R0
SYMATTR InstName C10
SYMATTR Value 100p
TEXT 846 522 Left 0 !.tran 0 20m 0 100n
TEXT 320 424 Left 0 !.param Cgain=1E5
TEXT 1272 432 Left 0 !.model ZD1 D(Vrev={Vsupp} Ron=.001)
TEXT 1272 512 Left 0 !.model Df D(Vfwd=0.6 Ron=0.027)
TEXT 1144 560 Left 0 !.model SW SW(Ron=0.225 Roff=1e9 Vt=0 Vh=-0.9)
TEXT 1336 392 Left 0 !.param Vsupp=50
TEXT 856 472 Left 0 !;op
TEXT -960 -256 Left 0 ;Gain = 0.2*(Vo_p - Vo_n)
TEXT 1272 472 Left 0 !.model ZD2 D(Vrev=10 Ron=.001)
TEXT -1232 -560 Left 0 !.params Rdiff=100k fc2=62.5k ; choose op-amp
resistors and V sample amp's cutoff
TEXT -1232 -520 Left 0 !.params kf={fc2/0.102431} ; compute freq.
scaling factor ; constant is the cutoff in Hz of a 2-pole prototype cascade
TEXT -1232 -480 Left 0 !.params C1diff={1/(Ro*kf)} C2diff={1/(Rdiff*kf)}
TEXT -1232 -720 Left 0 !.params Gain=5 ; choose total gain from input
to output terminals
TEXT -1232 -680 Left 0 !.params d={1/Gain} ; d is the division ratio of
the V sample dividers which is also the gain of the V sample amp stage
TEXT -1232 -640 Left 0 !.params Ro=500 ; choose the Thev. resistance
driving the differential amp inputs
TEXT -1232 -600 Left 0 !.params Rdiv1={Ro/d} Rdiv2={Ro/(1-d)} ;
compute required divider resistors
---------------------------------------------------------------

Comments and pointers appreciated, even despite foul language and insults.

Good day!

--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarleRemoveThis@BOGUSsandia.gov
NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.

Genome · Apr 12, 2005

"Chris Carlen" <crcarleRemoveThis@BOGUSsandia.gov> wrote in message
news:d3h35902uke@news4.newsguy.com...

Comments and pointers appreciated, even despite foul language and insults.

Good day!

No, Fucking crap, but I got pissed again so it's been ACE.

--
Christopher R. Carlen

Try

Version 4
SHEET 1 2256 1332
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FLAG -64 48 PHA
IOPIN -64 48 In
FLAG 832 48 PHB
IOPIN 832 48 In
FLAG -64 432 PHB
IOPIN -64 432 In
FLAG 832 432 PHA
IOPIN 832 432 In
FLAG -272 704 0
FLAG -64 240 PREA
IOPIN -64 240 Out
FLAG 832 240 PREB
IOPIN 832 240 Out
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IOPIN -64 176 Out
FLAG 832 176 POSTB
IOPIN 832 176 Out
FLAG -64 544 ISNSA
IOPIN -64 544 Out
FLAG 832 544 ISNSB
IOPIN 832 544 Out
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IOPIN 1136 1120 Out
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IOPIN -144 1072 Out
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FLAG 0 832 +15
IOPIN 0 832 Out
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IOPIN 1136 848 Out
FLAG 1136 1024 PHB
IOPIN 1136 1024 Out
FLAG -144 1024 VERR
IOPIN -144 1024 In
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IOPIN 832 0 Out
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IOPIN 1104 400 In
SYMBOL sw 48 128 M180
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SYMATTR InstName S1
SYMATTR Value MSW
SYMBOL sw 720 128 R180
WINDOW 0 72 65 Left 0
WINDOW 3 44 40 Left 0
SYMATTR InstName S2
SYMATTR Value MSW
SYMBOL sw 48 512 M180
WINDOW 0 41 67 Left 0
WINDOW 3 40 43 Left 0
SYMATTR InstName S3
SYMATTR Value MSW
SYMBOL sw 720 512 R180
WINDOW 0 78 68 Left 0
WINDOW 3 51 44 Left 0
SYMATTR InstName S4
SYMATTR Value MSW
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WINDOW 3 5 56 VBottom 0
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WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
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SYMBOL cap 400 160 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
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WINDOW 3 -44 27 Left 0
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SYMBOL diode 608 112 R180
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WINDOW 3 39 25 Left 0
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WINDOW 3 35 30 Left 0
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SYMATTR Value DID
SYMBOL diode 176 496 R180
WINDOW 0 -36 50 Left 0
WINDOW 3 -48 29 Left 0
SYMATTR InstName D3
SYMATTR Value DID
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WINDOW 3 -64 65 Left 0
SYMATTR InstName R2
SYMATTR Value 0R1
SYMBOL res 32 560 R0
WINDOW 3 36 66 Left 0
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SYMATTR Value 0R1
SYMBOL Digital\\CD4000\\CD4070B 704 976 R0
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WINDOW 3 -27 14 Left 0
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SYMATTR SpiceLine VDD=15 SPEED=1.0 TRIPDT=5e-9
SYMBOL Digital\\CD4000\\CD4050B 272 912 R0
SYMATTR InstName U3
SYMATTR SpiceLine VDD=15 SPEED=1.0 TRIPDT=5e-9
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SYMATTR InstName U4
SYMATTR SpiceLine VDD=15 SPEED=1.0 TRIPDT=5e-9
SYMBOL Digital\\CD4000\\CD4050B 560 912 R0
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SYMATTR SpiceLine VDD=15 SPEED=1.0 TRIPDT=5e-9
SYMBOL Digital\\CD4000\\CD4081B 1040 960 R0
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WINDOW 3 36 68 Left 0
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WINDOW 3 -193 67 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
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TEXT -280 744 Left 0 !.MODEL MSW SW(RON=10m ROFF=1E6 VT=5V VH=-2V)
TEXT -280 768 Left 0 !.MODEL DID D(RON=10m)
TEXT 24 1200 Left 0 !.tran 0 2m 1u uic
TEXT 24 1176 Left 0 !.include C:\\Program
Files\\LTC\\SwCADIII\\lib\\cmp\\Cd4000.lib
TEXT 24 1128 Left 0 !.MODEL COMP SW(RON=10m ROFF=1E6 VT=0 VH=1m)
TEXT 24 1152 Left 0 !.lib opamp.sub
TEXT -280 792 Left 0 !.MODEL ZID D(RON=10m VREV=2)

This is voltage mode control with feedback pre-filter.

Might fuck itself over.

Plot V(verr) along with V(vtri) and V(pha) along with V(phb) in a different
one.

Then reduce C1 and C2 to 1n5 and do it again.

The integrating amplifier converts its square wave input to a triangle wave.

If the slope at its output V(verr) exceeds that of the modulating triangle
wave, V(vtri) then.....

That sets a limit on the gain of the VEA.

I am proud to announce that I have been quite crap.

DNA

Chris Carlen · Apr 13, 2005

Genome wrote:
[edit]

This is voltage mode control with feedback pre-filter.

Might fuck itself over.

Plot V(verr) along with V(vtri) and V(pha) along with V(phb) in a different
one.

Then reduce C1 and C2 to 1n5 and do it again.

The integrating amplifier converts its square wave input to a triangle wave.

If the slope at its output V(verr) exceeds that of the modulating triangle
wave, V(vtri) then.....

That sets a limit on the gain of the VEA.

Ok, got it. This might enable me to substantially simplify matters.

Thanks.

I am proud to announce that I have been quite crap.

DNA

Not at all.

Good day!

--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarleRemoveThis@BOGUSsandia.gov
NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.

Genome · Apr 13, 2005

"Chris Carlen" <crcarleRemoveThis@BOGUSsandia.gov> wrote in message
news:d3hrf80o19@news4.newsguy.com...

Genome wrote:
[edit]
Ok, got it.
Thanks.

Good day!

--
Christopher R. Carlen

Burble, I wish I did.

No kidding.

With a 2V triangle in 4uS it does a dV/dT of 500,000V/S.

80V across 100K is 800uA. So.... C=800uA/500,000 or 1n6.

Which don't work so I doubled it.

I don't think I know how the diff integrator is working.

I think I might have done.

Where's me bed?

That's why I'm being crap.

But, now you know.

Cool

DNA

Nico Coesel · Apr 13, 2005

Chris Carlen <crcarleRemoveThis@BOGUSsandia.gov> wrote:

Besides, 225uH inductors and 72uF capacitors sound way too large to
me. I expect the inductors 10uH to 47uH and the capacitors from 1uF to
10uF.

I'm not bothering with the filter at all. My filter is reasonable, at
22.5uH and 7.2uH. Larry proposed making the values 10x larger in order
to demonstrate his post-filter compensation idea.

It is also true that the load inductance is likely to be non-linear due
to the fact that it is a PM linear motor. I don't expect perfect
performance from the filter. Nor should it be a problem because any of
the wigglies in the overall response are at much higher frequencies than
the application involves. The only time they will become relevant is in
other potential applications where the bandwidth approaches the limits
of the amp.

I suppose there is an outer loop which controls the speed/position of
the servo you are controlling through the class-D amplifier. I assume
this outer loop should flatten the closed loop frequency response of
the entire control system.
I think it is easier to achieve closed loop stability by placing
limits on the amplifiers input (bandwidth / gain) than at its output.

"In other words, butterworth, bessel and zobel look nice in theory,
but their practical use is very limited when it comes to class D
amplifiers.

I found out that using some inductors and capacitors to smear the
pulses into something that looks like a signal and using a common mode
filter as a final stage to get rid of the HF components works much
better."

Are you saying that you would incline toward overdamping the output
filter so that it's response is not so sensitive to load reactance, and
just accepting the increased ripple that would result?

I'm saying: treat the output like it is a switching PSU with a
synchronous rectifier and build the filter around a worst case
scenario (maximum current and allowable ripple). Then you know the
worst case signal from the output for whatever load is attached.
Using that knowledge you can choose whether further filtering is
required or not, but this choice is probably based on EMI requirements
and sensitivity to HF ripple of the load.

--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Larry Brasfield · Apr 10, 2005

"Larry Brasfield" <donotspam_larry_brasfield@hotmail.com>
wrote in message news

wT5e.13$AV3.440@news.uswest.net...

"Chris Carlen" <crobc@BOGUSFIELD.sbcglobal.net> wrote
in message news:d38qfa02aif@news4.newsguy.com...
....
My idea was that since I had to build an amp for about 3.5A RMS into the load of 2.5ohm+250uH
....

[re phase delay up to 150 Hz]

2 degrees.

I suppose I can translate that to flat delay within +/- 37 uS
from DC to 150 Hz and beyond that, don't care.
....
Is it a 2 pole LC LPF, nominally?

Yes.
....
My present load will be a 2.5 ohm coil with 250uH of inductance.
Thus the LC filter elements are 22.5uH and 7.2uF.
....
May I presume you are willing to use a 10% ceramic
cap and 5% gapped core set for the inductor? (This
may well be relaxed once the phase delay performance
is simulated or analyzed with respect to sensitivity.)

The design is not very sensitive considering the fairly
wide group delay band that is apparently allowed.
The above accuracy is likely to be excessive.

....

Having sketched a quick root-locus for this, I
am still convinced. I have two complex poles
in G, near the imaginary axis, and two zeros in
H near the real axis and about as far from the
origin as the LPF poles. (And some poles way
to the left to make it realizable.) With the right
loop gain, the poles move to the left and around
the zero pair, ending up just about wherever they
are most useful for that controlled delay filter I
mentioned.

What kind of DC accuracy do you need? Can
gain variation induced by 80V supply variation
be handled by an outer loop? Or does this power
amp have to have very tight gain and offset specs?
(Until it appears necessary, I hesitate to add a pole
at zero just to reduce maybe tolerable error.)

Upon further reflection, an integrator in the forward
path to get precise gain and offset is no big deal.
With a little tweaking to get the 3 poles properly
related to each other, the group delay easily falls
within a couple uS band out to 400 Hz. With even
more effort, (ajusting the zero positions and care
in setting loop gain), the 3 poles could be made to
conform to a cookbook equiripple group delay LPF.
From the initial results of simulation, I see no need
to bother with that mathematical exercise.

....

They will be designed to hold up at least 75% of their inductance to 10A.

Gapped parts would do better. If the open-loop
response can be kept more predictable, it will be
easier to control the close-loop phase delay. The
LC poles do not have to be kept so far out.

For the simulation included below, I set the LC poles
about 10 times closer to the origin, similar damping.
This should take down the ripple most of 40 dB. It
can work to set the filter higher, but the shifted poles
get closer to the switching frequency than I would
like to see.

So far I haven't dealt with any cases of having complex poles in the open loop, so this is virgin territory.

That's were it becomes fun. With a few more
answers, I am inclined to simulate a controller
and idealization of your plant.

Following is source for an LTSPice simulation
(see http://www.linear.com/company/software.jsp )
with the 2 zeroes and 1 pole in H, and 1 pole
at 0) in G. This is not any kind of final design,
but it does demonstrate how easy it will be to
attain the performance so far mentioned. For
a real circuit, there may need to be a bit more
filtering to keep switching junk out of the first
near-differentiator (or it may be fine as is). It
will certainly work to use slower op-amps.

========== begin lcyank.asc ==============
Version 4
SHEET 1 880 740
WIRE -528 496 -528 448
WIRE -512 240 -512 224
WIRE -512 336 -512 320
WIRE -496 448 -528 448
WIRE -496 528 -496 448
WIRE -480 448 -496 448
WIRE -480 528 -496 528
WIRE -432 224 -512 224
WIRE -432 240 -432 224
WIRE -432 336 -432 320
WIRE -368 448 -400 448
WIRE -368 528 -400 528
WIRE -352 448 -368 448
WIRE -352 528 -368 528
WIRE -336 224 -432 224
WIRE -256 320 -256 224
WIRE -256 496 -256 352
WIRE -240 320 -256 320
WIRE -240 352 -256 352
WIRE -224 224 -256 224
WIRE -144 224 -160 224
WIRE -144 336 -176 336
WIRE -144 336 -144 224
WIRE -96 336 -144 336
WIRE -80 336 -96 336
WIRE -80 496 -256 496
WIRE -80 496 -80 384
WIRE -64 496 -80 496
WIRE -32 192 -32 176
WIRE -32 288 -32 272
WIRE 16 176 -32 176
WIRE 16 384 0 384
WIRE 16 480 0 480
WIRE 16 480 16 384
WIRE 32 480 16 480
WIRE 32 512 0 512
WIRE 32 544 32 512
WIRE 48 176 16 176
WIRE 64 384 16 384
WIRE 144 480 112 480
WIRE 160 176 128 176
WIRE 160 240 160 176
WIRE 160 320 160 304
WIRE 192 176 160 176
WIRE 208 176 192 176
WIRE 208 384 144 384
WIRE 208 384 208 176
WIRE 208 480 208 384
WIRE 256 176 208 176
WIRE 256 192 256 176
WIRE 256 304 256 272
WIRE 256 400 256 384
FLAG -512 336 0
FLAG -32 288 0
FLAG 256 400 0
FLAG 160 320 0
FLAG -528 496 0
FLAG -368 448 VP
FLAG -208 304 VP
FLAG -32 464 VP
FLAG -368 528 VN
FLAG -32 528 VN
FLAG -208 368 VN
FLAG -432 224 VS
FLAG 192 176 VX
FLAG 16 176 VA
FLAG -96 336 VC
FLAG -432 336 0
FLAG 32 544 0
SYMBOL res 240 288 R0
SYMATTR InstName R1
SYMATTR Value 2.5
SYMBOL ind 240 176 R0
SYMATTR InstName L1
SYMATTR Value 250?
SYMBOL cap 144 240 R0
WINDOW 0 7 -9 Right 0
WINDOW 3 -7 24 Right 0
SYMATTR InstName C1
SYMATTR Value {7.2?/LPFS}
SYMBOL ind 32 192 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
SYMATTR InstName L2
SYMATTR Value {22.5?/LPFS}
SYMBOL Opamps\\LT1215 -32 432 M0
SYMATTR InstName U1
SYMBOL Opamps\\LT1215 -208 272 R0
SYMATTR InstName U2
SYMBOL bv -32 176 R0
WINDOW 3 30 -75 Left 0
SYMATTR InstName B1
SYMATTR Value V={GX*V(VC)}
SYMBOL voltage -512 224 R0
WINDOW 123 -25 94 Right 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0
SYMATTR Value2 AC 1
SYMBOL voltage -384 448 R90
WINDOW 0 -14 103 VBottom 0
WINDOW 3 4 10 VTop 0
SYMATTR InstName V2
SYMATTR Value 10
SYMBOL voltage -496 528 R270
WINDOW 0 -32 10 VTop 0
WINDOW 3 -4 100 VBottom 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL res -448 224 R0
SYMATTR InstName R2
SYMATTR Value 12k
SYMBOL cap 144 496 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C2
SYMATTR Value 1n
SYMBOL res 160 368 R90
WINDOW 0 -4 71 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R3
SYMATTR Value 12k
SYMBOL res 16 368 R90
WINDOW 0 11 19 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R4
SYMATTR Value 12k
SYMBOL cap -160 240 M270
WINDOW 0 23 7 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C3
SYMATTR Value 1n
SYMBOL res -352 208 M90
WINDOW 0 -3 73 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R5
SYMATTR Value 12k
SYMBOL res 128 464 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R6
SYMATTR Value 1k
TEXT -204 606 Left 0 !.ac oct 20 10 500k
TEXT -496 96 Left 0 !.step param GX 0 5 1
TEXT -496 128 Left 0 !.param LPFS=.1
========== end lcyank.asc ==============

The above simulation should be a convincing demonstration
that using the controller to get the PWM filtered output
response apparently desired by the OP is feasable and
unlikely to present serious problems. Obviously, gains
and maybe offsets will need adjustment once the VCVS
is replaced by the PWM IC. When current limiting is put
into place, some attention to limiting in the controller will
be in order. A sensitivity analysis for L and C variation
would be smart. It might be a good idea to make sure
no limit cycles are possible, using time domain simulation
and a range of step inputs.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

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