Problem in ALUControl

[Muhammadreza Haghiri]

I wrote an ALUControl for MIPS ECE4680 : https://github.com/prp-e/ECE4680/blob/master/ALUControl.v

When I want to compile it, verilog says :

ALUControl.v:4: syntax error
ALUControl.v:4: error: Invalid variable list in port declaration.

What's wrong in 4th line?

 

[Gunjan]

On Tuesday, December 8, 2015 at 11:10:27 AM UTC-8, Muhammadreza Haghiri wrote:

I wrote an ALUControl for MIPS ECE4680 : https://github.com/prp-e/ECE4680/blob/master/ALUControl.v

When I want to compile it, verilog says :

ALUControl.v:4: syntax error
ALUControl.v:4: error: Invalid variable list in port declaration.

What's wrong in 4th line?

Your 4th line should be as follows

output reg [3:0] ALUCtl; //the reg keyword should be after output and not after the size.

 

[GaborSzakacs]

Gunjan wrote:

On Tuesday, December 8, 2015 at 11:10:27 AM UTC-8, Muhammadreza Haghiri wrote:
I wrote an ALUControl for MIPS ECE4680 : https://github.com/prp-e/ECE4680/blob/master/ALUControl.v

When I want to compile it, verilog says :

ALUControl.v:4: syntax error
ALUControl.v:4: error: Invalid variable list in port declaration.

What's wrong in 4th line?


Your 4th line should be as follows

output reg [3:0] ALUCtl; //the reg keyword should be after output and not after the size.

Some other notes:

always case (FuncCode)
32: ALUCt1 <= 2;
. . .

This process has no sensitivity list, which will hang in simulation.
In addition, all assignments are non-blocking. This makes no difference
to synthesis, however it will probably cause simulation to crash due
to memory usage for continuously scheduling the same assignments. At
least that's been my experience with ModelSim.

I'd suggest writing this like:

always @* // Implied sensitivity list equivalent to always @ (FuncCode)
case (FuncCode)
32: ALUCt1 = 2; // Blocking assignments are appropriate for
combinatorial process
. . .
default: ALUCt1 = 7;
endcase

--
Gabor