Post synthesis(PAR) Simln in Xilinx WEbPack 5.2: Port Mismat

[Sriram]

hi ,
I was able to do compile and do behavioral simulation of the matrix
addition code. Then I synthesized it using Xilinx WebPack ISE 5 tools .
Then when I try to use tbw (test bench waveform ) am unable to create
one as my input matrices are "array of arrays" type . So I wrote my own
testbench .
Using this I was able to do behav simln,
But when I tried to do post Place and route Simulation , I ran into
errors .
the Error messages I run into are :
# WARNING[1] :types do not match for port a_mat
# WARNING[1]: matadd_Xilinx_tb.vhd(44): A use of this default binding
for this component instantiation will result in an elaboration error.

My guess is that the synthesized output doesnt recognize matrix_type as
a valid type and so the design's a_mat and the testbench' s a_mat dont
match,resulting in the above port mismatch error.

I'm able to zero in on why the error is occuring , but since XILINX has
hidden the synthesis and implementation processes , dont know how to
rectify the above port mismatch problem.

If anybody in the group , has encountered a similar problem and know
the fix to it , it would be immensely helpful .

thanks ,
Sriram



My source code for design and testbench are :
PACKAGE :

library ieee;
use ieee.std_logic_1164.all;
package matrix_types is
constant matwidth : positive := 2; --Matrix Width
TYPE matrix_type IS ARRAY (matwidth-1 DOWNTO 0) OF
STD_LOGIC_VECTOR(matwidth -1 DOWNTO 0);
end;

MAtrix addition design code :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all ;
use work.matrix_types.all;
ENTITY matrix_add IS
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
A_mat : in matrix_type;
B_mat : in matrix_type;
Sum_mat : out matrix_type
);
END matrix_add;
ARCHITECTURE behav OF matrix_add IS
BEGIN
-- matrix addition
behav_pr: process (A_mat,B_mat,clock,reset)
begin
if (reset='1') then
Sum_mat <= (others => (others=>'0') );
elsif(clock'event and clock ='1') then
for i in matwidth -1 downto 0 loop
sum_mat(i) <= std_logic_vector (unsigned(A_mat(i)) +
unsigned(B_mat(i))) ;
end loop ;
end if ;
end process behav_pr;
end architecture behav ;

My testbench :

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.matrix_types.all;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT matrix_add
PORT(
reset : IN std_logic;
clock : IN std_logic;
a_mat : IN matrix_type;
b_mat : IN matrix_type;
sum_mat :OUT matrix_type
);
END COMPONENT;
SIGNAL reset : std_logic;
SIGNAL clock : std_logic;
SIGNAL a_mat : matrix_type;
SIGNAL b_mat : matrix_type;
SIGNAL sum_mat :matrix_type;
BEGIN
uut: matrix_add PORT MAP(
reset => reset,
clock => clock,
a_mat => a_mat,
b_mat => b_mat,
sum_mat => sum_mat
);

-- *** Test Bench - User Defined Section ***
rst_prrocess
begin
reset<='1';
wait for 4 ns ;
reset<='0';
wait ;
end process rst_pr ;
------------------------
-- clock process
-----------------------
clk_pr rocess
begin
clock <='1';
wait for 10 ns ;
clock <='0';
wait for 10 ns ;
end process clk_pr ;
------------------------
-- inputs process
-----------------------
inputs_prrocess
begin
a_mat <= ( ("00") ,("00") ) ;
b_mat <= ( ("11") ,("11") ) ;
wait for 35 ns ;
a_mat <= ( ("00") ,("01") ) ;
b_mat <= ( ("11") ,("01") ) ;
wait for 10 ns;
a_mat <= ( ("01") ,("00") ) ;
b_mat <= ( ("11") ,("00") ) ;
wait ;
end process inputs_pr;
-- *** End Test Bench - User Defined Section ***
END;