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OK, pointy-haired boss question.
Given a ZYNQ 7020, speed grade 1. A 3.3 volt i/o bank gets a clock
from an LVDS input. We have a resync flop in an i/o cell, clocked by
this, with a D input from somewhere. Output is the strongest/fastest
3.3 volt option.
About what would be the typical prop delay from the clock to the
output pin?
Online search yields a lot of words and no numbers. Experts say useful
things like \"it depends.\" The tools apparently give a range of timings
over worst-case supply voltage, process, and temperature that vary by
about 4:1 with no typical.
Second question: has anyone ever pushed an FPGA core voltage up to get
more speed? In one little test I did, on an Artix 7, a simple case
changed chip prop delay by 1 ns, from about 8.5 to about 7.5 ns, with
a 70 mV core supply increase. That delay was essentially all
combinational.
--
John Larkin Highland Technology, Inc
The best designs are necessarily accidental.
Given a ZYNQ 7020, speed grade 1. A 3.3 volt i/o bank gets a clock
from an LVDS input. We have a resync flop in an i/o cell, clocked by
this, with a D input from somewhere. Output is the strongest/fastest
3.3 volt option.
About what would be the typical prop delay from the clock to the
output pin?
Online search yields a lot of words and no numbers. Experts say useful
things like \"it depends.\" The tools apparently give a range of timings
over worst-case supply voltage, process, and temperature that vary by
about 4:1 with no typical.
Second question: has anyone ever pushed an FPGA core voltage up to get
more speed? In one little test I did, on an Artix 7, a simple case
changed chip prop delay by 1 ns, from about 8.5 to about 7.5 ns, with
a 70 mV core supply increase. That delay was essentially all
combinational.
--
John Larkin Highland Technology, Inc
The best designs are necessarily accidental.