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David Rogoff
Guest
Hi all. More VHDL headaches. I've been using a lot of overloaded procedures - mostly to deal with optional arguments / default values that VHDL does not support. So far, so good. However, I need multiple versions of a procedure that take an std_logic_vector as an input but with different widths. I have something like the following:
subtype shortdata_t is std_logic_vector (7 downto 0);
subtype meddata_t is std_logic_vector (15 downto 0);
procedure a (d_in : in shortdata_t; .....);
procedure a (d_in : in meddata_t; .....);
This just gets me illegal redeclaration errors from the compiler. I think it's because they're different subtypes, not different types. I could use a generic and pass the size but that's a big headache. Is there a way to do this?
Also, is there a way (or upcoming standard) to have optional inputs with default values like SystemVerilog so I don't have to have multiple, overloaded versions of subprograms just to deal with that?
Thanks,
David
subtype shortdata_t is std_logic_vector (7 downto 0);
subtype meddata_t is std_logic_vector (15 downto 0);
procedure a (d_in : in shortdata_t; .....);
procedure a (d_in : in meddata_t; .....);
This just gets me illegal redeclaration errors from the compiler. I think it's because they're different subtypes, not different types. I could use a generic and pass the size but that's a big headache. Is there a way to do this?
Also, is there a way (or upcoming standard) to have optional inputs with default values like SystemVerilog so I don't have to have multiple, overloaded versions of subprograms just to deal with that?
Thanks,
David