Overloading procedures with parameters of different size?

D

David Rogoff

Guest
Hi all. More VHDL headaches. I've been using a lot of overloaded procedures - mostly to deal with optional arguments / default values that VHDL does not support. So far, so good. However, I need multiple versions of a procedure that take an std_logic_vector as an input but with different widths. I have something like the following:

subtype shortdata_t is std_logic_vector (7 downto 0);
subtype meddata_t is std_logic_vector (15 downto 0);


procedure a (d_in : in shortdata_t; .....);

procedure a (d_in : in meddata_t; .....);

This just gets me illegal redeclaration errors from the compiler. I think it's because they're different subtypes, not different types. I could use a generic and pass the size but that's a big headache. Is there a way to do this?

Also, is there a way (or upcoming standard) to have optional inputs with default values like SystemVerilog so I don't have to have multiple, overloaded versions of subprograms just to deal with that?

Thanks,

David
 
On Thu, 12 Feb 2015 14:44:47 -0800, David Rogoff wrote:

Hi all. More VHDL headaches. I've been using a lot of overloaded
procedures - mostly to deal with optional arguments / default values
that VHDL does not support. So far, so good. However, I need multiple
versions of a procedure that take an std_logic_vector as an input but
with different widths. I have something like the following:

subtype shortdata_t is std_logic_vector (7 downto 0);
subtype meddata_t is std_logic_vector (15 downto 0);


procedure a (d_in : in shortdata_t; .....);

procedure a (d_in : in meddata_t; .....);

This just gets me illegal redeclaration errors from the compiler. I
think it's because they're different subtypes, not different types. I
could use a generic and pass the size but that's a big headache. Is
there a way to do this?

Also, is there a way (or upcoming standard) to have optional inputs with
default values like SystemVerilog so I don't have to have multiple,
overloaded versions of subprograms just to deal with that?

Thanks,

David

There's always

procedure a (d_in : std_logic_vector; .....) is
begin
if d_in'length = shortdata_t'length then
....

Inelegant, but it would get the job done.


--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.
 
On Thursday, February 12, 2015 at 5:44:48 PM UTC-5, David Rogoff wrote:
Also, is there a way (or upcoming standard) to have optional inputs with default values like SystemVerilog so I don't have to have multiple, overloaded versions of subprograms just to deal with that?

Yes, you just put the default value in the procedure declaration:

The following defaults the value of 'd_in' to "00000000"
procedure a (d_in : std_logic_vector "= x"00"; .....)

Kevin Jennings
 
On Thu, 12 Feb 2015 14:44:47 -0800, David Rogoff wrote:

Hi all. More VHDL headaches. I've been using a lot of overloaded
procedures - mostly to deal with optional arguments / default values
that VHDL does not support. So far, so good. However, I need multiple
versions of a procedure that take an std_logic_vector as an input but
with different widths. I have something like the following:

subtype shortdata_t is std_logic_vector (7 downto 0);
subtype meddata_t is std_logic_vector (15 downto 0);


procedure a (d_in : in shortdata_t; .....);

procedure a (d_in : in std_logic_vector; .....);

Make the body of "a" agnostic about d_in's actual length, using
attributes where necessary, "for i in d_in'range loop ..." etc.
If you need to identify the actual subtype, Rob's trick of testing
d_in'length in an if or case statement will work.


-- Brian
 
Thanks - Unfortunately, this will only work with named associations in the procedure/function call. In general, I'm in favor of this, but when you have hundreds of calls of the same procedure that each have long lists of arguments, it can be get really messy. Does it work for positional associations if the optional argument is the last one?

David
 
On 13/02/15 19:15, David Rogoff wrote:
Thanks - Unfortunately, this will only work with named associations in the procedure/function call. In general, I'm in favor of this, but when you have hundreds of calls of the same procedure that each have long lists of arguments, it can be get really messy. Does it work for positional associations if the optional argument is the last one?

David
Yes, you can mix positional and named association, as long as positional
association comes first. You can't change back to positional association
after you've started named assocation.

regards
Alan

--
Alan Fitch
 

Welcome to EDABoard.com

Sponsor

Back
Top