output <= registers(to_integer(address)) and intentional met

Hi,
I have an array of std_logic_vectors. The address selector (unsigned type) may intentionally be unsigned to don't care/unknown state in order to simplify logic in other parts of a design. In such a case, the simulator will generate a warning, however, the output vector will be assigned to registers(0). My intention, in such a case, would be to assign don't care/unknown state also to the output vector. Is there any best practice for this problem?
I know that something like:
output &lt;= (others =&gt; '-') when is_x(address) else registers(to_integer(address));
could work, but according to my knowledge, the is_x function may have a problem with synthesis.

Another option would be to write a process:

mux: process(all)
begin
output &lt;= (others =&gt; '-');
for i in registers'range loop
if address = to_unsgined(i, address'range) then
output &lt;= registers(i);
end if;
end loop;
end process;

However, I am worried that the synthesis tool may have an issue to extract a proper and simple mux from this description.

Is there any more straightforward description? I am using VHDL 2008.

Regards,
Adrian

 

[Rick C]

On Tuesday, June 18, 2019 at 8:43:46 AM UTC-4, a.fie...@gmail.com wrote:

Hi,
I have an array of std_logic_vectors. The address selector (unsigned type) may intentionally be unsigned to don't care/unknown state in order to simplify logic in other parts of a design. In such a case, the simulator will generate a warning, however, the output vector will be assigned to registers(0). My intention, in such a case, would be to assign don't care/unknown state also to the output vector. Is there any best practice for this problem?
I know that something like:
output &lt;= (others =&gt; '-') when is_x(address) else registers(to_integer(address));
could work, but according to my knowledge, the is_x function may have a problem with synthesis.

Another option would be to write a process:

mux: process(all)
begin
output &lt;= (others =&gt; '-');
for i in registers'range loop
if address = to_unsgined(i, address'range) then
output &lt;= registers(i);
end if;
end loop;
end process;

However, I am worried that the synthesis tool may have an issue to extract a proper and simple mux from this description.

Is there any more straightforward description? I am using VHDL 2008.

Regards,
Adrian

Why not convert address to an integer and use it as the index in a simple assignment? Put that assignment inside a conditional that checks the bounds of the register index and perform the default assignment if that test fails.

output &lt;= registers(to_integer(address)) when
(to_integer(address) in registers'range) else
output &lt;= (others =&gt; '-');

Not sure if (to_integer(address) in registers'range) is a valid expression for this syntax. You may need to break that out as an AND of the upper and lower limit checks.

The way to see what the compiler does with this syntax is to construct a test bench that simply instantiates the code and look at the result in your synthesis tool. I would do that with your existing code before bothering to optimize it.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

Hi Rick,

Thank you for your reply.

I haven't simulated it, but as you propose to_integer(address) you will have the same issue: even if the address has meta values, the output of the to_integer will be 0 which lies in the range of registers.

 

[Rick C]

On Tuesday, June 18, 2019 at 9:47:10 AM UTC-4, a.fie...@gmail.com wrote:

Hi Rick,

Thank you for your reply.

I haven't simulated it, but as you propose to_integer(address) you will have the same issue: even if the address has meta values, the output of the to_integer will be 0 which lies in the range of registers.

Sorry, I didn't quite catch what you had written. i assume this conditional is intended only for simulation and debug and has nothing to do with the operation of the circuit since these values are not synthesizable.

In that case, simply substitute the is_X function for the comparison in the WHEN conditional and it should do what you want... assuming I now understand the full problem.

I see in your original post you talk about IS_X not being synthesizable, so I'm wondering if you really are trying to synthesize the use of meta-values. If you give it a bit of thought you will realize there is no hardware that will perform this sort of evaluation, so the use of meta-values can't generate synthesizable logic. I believe constructs like these are simply ignored by synthesis.

I shouldn't make this sound so absolute though. I believe the value '-' can be used in comparisons as a wild card, but it has been too long since I've done this to remember if it is limited to non-standard extensions of synthesizers. After digging a bit, I see VHDL-2008 allows wild cards to be used in a version of case statements.

Am I getting closer to understanding your question?

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

Yes, I think you are getting closer to the core of the issue.

You are right, this condition is intended only for the simulation. I want to avoid a mismatch between eventual hardware and the behavioural verification: when address is unknown, also the "output" vector should be unknown. Currently, in simulation, it will be assigned to registers(0) (to_integer returns 0 for vectors containing meta value bits). An RTL description being verified may rely on this fact (registers(0) output when address is don't care) and I would like to exclude it

My concern is that line like:
output &lt;= (others =&gt; '-') when is_x(address) else registers(to_integer(address));
will be fully ignored by a synthesis tool. I think, in general, synthesis tool's behaviour is not standardized in such a case.

I also confirm VHDL2008 comes with new relational operators (?=, ?&lt;...) and case? statements.

 

[Rob Gaddi]

On 6/18/19 5:43 AM, a.fiergolski@gmail.com wrote:

Hi,
I have an array of std_logic_vectors. The address selector (unsigned type) may intentionally be unsigned to don't care/unknown state in order to simplify logic in other parts of a design. In such a case, the simulator will generate a warning, however, the output vector will be assigned to registers(0). My intention, in such a case, would be to assign don't care/unknown state also to the output vector. Is there any best practice for this problem?
I know that something like:
output &lt;= (others =&gt; '-') when is_x(address) else registers(to_integer(address));
could work, but according to my knowledge, the is_x function may have a problem with synthesis.

Another option would be to write a process:

mux: process(all)
begin
output &lt;= (others =&gt; '-');
for i in registers'range loop
if address = to_unsgined(i, address'range) then
output &lt;= registers(i);
end if;
end loop;
end process;

However, I am worried that the synthesis tool may have an issue to extract a proper and simple mux from this description.

Is there any more straightforward description? I am using VHDL 2008.

Regards,
Adrian

I've definitely used IS_X in synthesizable code for exactly this reason, and
done pretty much exactly what you did (I tend to prefer 'X' to '-' as an output
don't care and only use '-' as an input don't care). It worked out just fine;
IS_X was treated as a constant false and the entire half of the condition
dropped out of existence.


--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

 

[Rick C]

On Tuesday, June 18, 2019 at 12:29:31 PM UTC-4, a.fie...@gmail.com wrote:

Yes, I think you are getting closer to the core of the issue.

You are right, this condition is intended only for the simulation. I want to avoid a mismatch between eventual hardware and the behavioural verification: when address is unknown, also the "output" vector should be unknown. Currently, in simulation, it will be assigned to registers(0) (to_integer returns 0 for vectors containing meta value bits). An RTL description being verified may rely on this fact (registers(0) output when address is don't care) and I would like to exclude it

My concern is that line like:
output &lt;= (others =&gt; '-') when is_x(address) else registers(to_integer(address));
will be fully ignored by a synthesis tool. I think, in general, synthesis tool's behaviour is not standardized in such a case.

I also confirm VHDL2008 comes with new relational operators (?=, ?&lt;...) and case? statements.

Why not just write a test case and try it with your tools. Most synthesis tools will let you "see" the resulting logic in diagrams which are easy to analyze as long as they aren't large.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

I confirm that my original idea (and confirmed by Rob as well) works:

[code:1:32d0a537f0]
output &lt;= registers&#40;to_integer&#40;address&#41;&#41; when not Is_X&#40;address&#41; else &#40;others =&gt; 'U'&#41;;
[/code:1:32d0a537f0]
I checked results generated by the synthesis tool, and it seems that it properly ignores (set False) Is_X branch and the generated netlist is equivalent to simple
[code:1:32d0a537f0]
output &lt;= registers&#40;to_integer&#40;address&#41;&#41;;
[/code:1:32d0a537f0]

Thank you all for discussion.