Multiplier using 1 bit full adder

I have a problem to build a multiplier. But it seems something wrong with my code that the output did not update. Anyone can help me?

My code is as followed
--multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Multiplier_VHDL is
GENERIC (WIDTH:INTEGER);
PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0));
end entity Multiplier_VHDL;

architecture Behavioral of Multiplier_VHDL is
signal a_temp:std_logic_vector(width-1 downto 0);
signal b_temp:std_logic_vector(width-1 downto 0);
signal mid:std_logic_vector(2*width-1 downto 0):=(others=>'0');
signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0');
signal cout_mid:std_logic_vector(2*width downto 0):=(others=>'0');
signal y_temp:std_logic_vector(2*width-1 downto 0);
begin
proc_multiplier1:
process(a_temp,b_temp)
begin
a_temp<=a;
b_temp<=b;
calculation_out:
for i in 0 to width-1 loop
if b_temp(i)='1' then
mid(width-1+i downto i)<=a_temp;
end if;
calculation_in:
for j in 0 to 2*width-1 loop
y_temp(j)<=mid_temp(j) xor mid(j) xor cout_mid(j);
cout_mid(j+1)<=(mid_temp(j) and mid(j)) or (mid_temp(j) and cout_mid(j)) or (cout_mid(j) and mid(j));
end loop calculation_in;
mid_temp<=y_temp;
cout_mid<=(others=>'0');
mid<=(others=>'0');
end loop calculation_out;

end process;

y<=y_temp;

end architecture Behavioral;

There is a warning message
Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf

 

[rickman]

On 10/1/2015 1:04 PM, zhangth1991@gmail.com wrote:

I have a problem to build a multiplier. But it seems something wrong with my code that the output did not update. Anyone can help me?

My code is as followed
--multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Multiplier_VHDL is
GENERIC (WIDTH:INTEGER);
PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0));
end entity Multiplier_VHDL;

architecture Behavioral of Multiplier_VHDL is
signal a_temp:std_logic_vector(width-1 downto 0);
signal b_temp:std_logic_vector(width-1 downto 0);
signal mid:std_logic_vector(2*width-1 downto 0):=(others=>'0');
signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0');
signal cout_mid:std_logic_vector(2*width downto 0):=(others=>'0');
signal y_temp:std_logic_vector(2*width-1 downto 0);
begin
proc_multiplier1:
process(a_temp,b_temp)
begin
a_temp<=a;
b_temp<=b;
calculation_out:
for i in 0 to width-1 loop
if b_temp(i)='1' then
mid(width-1+i downto i)<=a_temp;
end if;
calculation_in:
for j in 0 to 2*width-1 loop
y_temp(j)<=mid_temp(j) xor mid(j) xor cout_mid(j);
cout_mid(j+1)<=(mid_temp(j) and mid(j)) or (mid_temp(j) and cout_mid(j)) or (cout_mid(j) and mid(j));
end loop calculation_in;
mid_temp<=y_temp;
cout_mid<=(others=>'0');
mid<=(others=>'0');
end loop calculation_out;

end process;

y<=y_temp;

end architecture Behavioral;

There is a warning message
Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf

I don't know what this warning is about. Any chance you have two copies
of the simulator running?

I don't understand your code. I see one error. Your process
sensitivity list includes two signals that are updated within the
process. I think you meant to use a and b in the sensitivity list, no?

You need to run your code in the simulator and explore the various
signals to see if the code is doing what you need. Posting code here to
look for some silly mistakes is ok, but no one is likely to debug your
code for you. I'm not even sure how it is supposed to work. You seem
to have a lot of extraneous signals for a simple multiplier.

--

Rick

 

[GaborSzakacs]

zhangth1991@gmail.com wrote:

I have a problem to build a multiplier. But it seems something wrong with my code that the output did not update. Anyone can help me?

My code is as followed

[code snipped]

There is a warning message
Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf

That warning is something I've run into a lot with ModelSim, especially
older versions. It probably has nothing to do with your problems, as
ModelSim will simply create a WLF file with some random name and use
it instead of "vsim.wlf" I seem to recall this happens after you have
run some number of different projects and not cleaned up the old
vsim.wlf files. By the way, these files can get quite large and it
is usually worth it to remove them when you are done with a project
to reclaim the disk space.

--
Gabor

 

The problem is I dont know why I cannot assign y<=y_temp when a and b change the value

 

[HT-Lab]

On 01/10/2015 18:04, zhangth1991@gmail.com wrote:
...

There is a warning message
Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf

This happens when your simulation crashes, it sets a lock bit in the
vsim.wlf file which prevents Modelsim from overwriting it (vsim.wlf is
the default name). You can load the vsim.wlf file (vsim -view vsim.wlf)
and see what lead to the crash (or get close to it). You need to delete
the vsim.wlf file as Modelsim will continue to create new wlfxxxx files
until the file is deleted,

Hans
www.ht-lab.com


02/10/2015 09:18 1,387 transcript
03/09/2015 20:21 49,152 vsim.wlf
03/11/2005 12:21 1,105 wave.do
04/09/2015 17:38 786,432 wlft1sddnc
06/09/2015 20:52 57,344 wlftgbhqzx
10/09/2015 11:35 540,672 wlftiqcymw
16/09/2015 15:17 57,344 wlftq4i743
09/09/2015 17:54 778,240 wlftq5mdd3
08/09/2015 17:44 49,152 wlftqe9ds1
05/09/2015 12:55 57,344 wlftr57znr
27/08/2015 13:59 <DIR> work
16/11/2005 15:11 34 zoom.tcl
27 File(s) 2,949,498 bytes
4 Dir(s) 487,531,675,648 bytes free

 

[GaborSzakacs]

zhangth1991@gmail.com wrote:
> The problem is I dont know why I cannot assign y<=y_temp when a and b change the value

For simulation, only items in the process sensitivity
will "change the value." In your main process, you
only have a_temp and b_temp in the sensitivity list.
Since these are only assigned within the process, and
the process needs them to change in order to actually
run, then the process never triggers and all your outputs
remain undefined. You need to have a and b in the sensitivity
list to trigger the process. Also it is likely that you really
wanted a_temp and b_temp to be variables rather than signals.

--
Gabor

 

[rickman]

On 10/2/2015 9:26 AM, GaborSzakacs wrote:

zhangth1991@gmail.com wrote:
The problem is I dont know why I cannot assign y<=y_temp when a and b
change the value

For simulation, only items in the process sensitivity
will "change the value." In your main process, you
only have a_temp and b_temp in the sensitivity list.
Since these are only assigned within the process, and
the process needs them to change in order to actually
run, then the process never triggers and all your outputs
remain undefined. You need to have a and b in the sensitivity
list to trigger the process. Also it is likely that you really
wanted a_temp and b_temp to be variables rather than signals.

I've already told him his sensitivity list is wrong. Maybe he didn't
see my message. a_temp and b_temp really aren't needed. They are never
reassigned, so they are just duplicates of a and b. He should just use
a and b in the expressions instead of a_temp and b_temp.

I'm not sure what he is doing with this code actually. He seems to be
intending a bit serial adder, but rather than describing a shifter with
a one bit adder, he is describing a standard parallel addition, one bit
at a time, without a clock.

--

Rick