May Have to Learn Verilog...

R

Rick C

Guest
I\'ve nothing against Verilog, I\'ve been meaning to learn it for years now, but just never got my focus on the task. I\'m working with the Gowin devices and decided to try synthesis to see just how some of my constructs are going to be generated. The native Gowin synthesis tool doesn\'t seem to support VHDL. Either that or they give some very strange error messages.

Info (EXT0100) : Run analyzation & elaboration
Error (EXT3044) : Analyze: cannot read format vhdl in this product
Error (EXT3044) : Analyze: cannot read format vhdl in this product

Is analyzation even a word? It gets less than 1 million hits in Google while Analysis gets 2.5 BILLION. I guess it is a work, just not one people use much.

Anyway... the tool will invoke the Synplify tool, but I don\'t seem to have a license at the moment. I\'ve sent an email about this to the FAE contact. I should hear something by Monday. I\'m a bit disappointed in that no one mentioned this even with having asked questions about VHDL coding styles. I would have expected someone to say, \"Yeah, that will infer what you are looking for... but not with our tools. You\'ll have to spend a couple of kilobucks for your own copy of Synopsis tools.\"

If I need to convert my code from VHDL to Verilog, I\'m going to need a lot of hand holding. My main areas of concern is in knowing about the various assumptions the tool makes when doing arithmetic operations and test benches. I\'ve asked before about good books to help a guy out. The frequent reply is none seem to hit all the bases.

I used Verilog about 20 years ago and test benches were rather awkward to say the least. I\'m sure they\'ve improved, but I think that\'s going to be a bit of a learning curve.

Well, I guess I\'ll cross that bridge once I come to it. Hopefully there will be good news on Monday.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
 
On 17/10/2020 22:11, Rick C wrote:
I\'ve nothing against Verilog, I\'ve been meaning to learn it for years now, but just never got my focus on the task. I\'m working with the Gowin devices and decided to try synthesis to see just how some of my constructs are going to be generated. The native Gowin synthesis tool doesn\'t seem to support VHDL. Either that or they give some very strange error messages.

Info (EXT0100) : Run analyzation & elaboration
Error (EXT3044) : Analyze: cannot read format vhdl in this product
Error (EXT3044) : Analyze: cannot read format vhdl in this product

Is analyzation even a word? It gets less than 1 million hits in Google while Analysis gets 2.5 BILLION. I guess it is a work, just not one people use much.

Anyway... the tool will invoke the Synplify tool, but I don\'t seem to have a license at the moment. I\'ve sent an email about this to the FAE contact. I should hear something by Monday. I\'m a bit disappointed in that no one mentioned this even with having asked questions about VHDL coding styles. I would have expected someone to say, \"Yeah, that will infer what you are looking for... but not with our tools. You\'ll have to spend a couple of kilobucks for your own copy of Synopsis tools.\"

If I need to convert my code from VHDL to Verilog, I\'m going to need a lot of hand holding. My main areas of concern is in knowing about the various assumptions the tool makes when doing arithmetic operations and test benches. I\'ve asked before about good books to help a guy out. The frequent reply is none seem to hit all the bases.

I used Verilog about 20 years ago and test benches were rather awkward to say the least. I\'m sure they\'ve improved, but I think that\'s going to be a bit of a learning curve.

Well, I guess I\'ll cross that bridge once I come to it. Hopefully there will be good news on Monday.
Click to expand...
The Gowin synthesis tool works on VHDL for me.
If you want to email me at mk@mkesc
I\'ll send you a Dropbox link.
Add .co.uk to the other bit of the address.

MK
 
On Sunday, October 18, 2020 at 10:28:20 AM UTC-4, Michael Kellett wrote:
On 17/10/2020 22:11, Rick C wrote:
I\'ve nothing against Verilog, I\'ve been meaning to learn it for years now, but just never got my focus on the task. I\'m working with the Gowin devices and decided to try synthesis to see just how some of my constructs are going to be generated. The native Gowin synthesis tool doesn\'t seem to support VHDL. Either that or they give some very strange error messages.

Info (EXT0100) : Run analyzation & elaboration
Error (EXT3044) : Analyze: cannot read format vhdl in this product
Error (EXT3044) : Analyze: cannot read format vhdl in this product

Is analyzation even a word? It gets less than 1 million hits in Google while Analysis gets 2.5 BILLION. I guess it is a work, just not one people use much.

Anyway... the tool will invoke the Synplify tool, but I don\'t seem to have a license at the moment. I\'ve sent an email about this to the FAE contact. I should hear something by Monday. I\'m a bit disappointed in that no one mentioned this even with having asked questions about VHDL coding styles. I would have expected someone to say, \"Yeah, that will infer what you are looking for... but not with our tools. You\'ll have to spend a couple of kilobucks for your own copy of Synopsis tools.\"

If I need to convert my code from VHDL to Verilog, I\'m going to need a lot of hand holding. My main areas of concern is in knowing about the various assumptions the tool makes when doing arithmetic operations and test benches. I\'ve asked before about good books to help a guy out. The frequent reply is none seem to hit all the bases.

I used Verilog about 20 years ago and test benches were rather awkward to say the least. I\'m sure they\'ve improved, but I think that\'s going to be a bit of a learning curve.

Well, I guess I\'ll cross that bridge once I come to it. Hopefully there will be good news on Monday.

The Gowin synthesis tool works on VHDL for me.
If you want to email me at mk@mkesc
I\'ll send you a Dropbox link.
Add .co.uk to the other bit of the address.

MK
Click to expand...

Thanks for your reply.

I figured it out. I was using a version from some months ago. VHDL was just added recently. Now I was trying to examine the efficiency of synthesis with code to obtain the carry out of a down counter to allow it to be stopped at zero as you might want in a timing circuit or a state machine. I couldn\'t find a way to visualize a schematic for the results of synthesis. Turns out I still didn\'t have the most recent version, 1.9.7beta which does have the schematic viewer.

Now I just need a way to change the colors in the schematic. They use a neon cyan color for nets that is very hard to see. They also use such a small font on the connection labels that I have to zoom in so much to read them, I can\'t see the schematic with any perspective. It\'s better than reading the durn net list, but not by a lot.

The results of the survey are...

Everyone (Lattice, Synplify Pro for Lattice and Gowin) gets the same results after I got it all working. Three designs give a register and adder for each bit in the counter plus one for the carry. The fourth approach generates some extra logic to detect the current value of the counter being zero directly using LUTs.

The approach that requires the least amount of code without producing the extra logic requires an assignment to an aggregate which the ActiveHDL simulator barfs on at run time with a strange complaint about mismatched indices.. If it were a true mismatch I would expect the error to be flagged before the code is run. So maybe this is an Aldec error.

constant Cntr_Width : positive := 13;
constant Cntr_Modulus : positive := 2**Cntr_Width;
signal Count, nxt_cnt : unsigned(Cntr_Width - 1 downto 0) := (others => \'0\');
signal Count_a, nxt_cnt_a : unsigned(Cntr_Width - 1 downto 0) := (others => \'0\');
signal Count_e, nxt_cnt_e : natural range 0 to (Cntr_Modulus - 1) := 0;
begin

Down_Cntr (Count, nxt_cnt, Carry_Out);

test_sig: process (Clk) is
begin
if rising_edge(Clk) then
Test_Out <= Carry_Out;
if (Cnt_En OR not Carry_Out) then
Count <= nxt_cnt;
end if;
end if;
end process test_sig;

Carry_Out_e <= \'1\' when Count_e = 0 else \'0\'; -- produces an N wide OR

test_eq: process (Clk) is
begin
if rising_edge(Clk) then
Test_Out_e <= Carry_Out_e;
if (Cnt_En OR not Carry_Out_e) then
Count_e <= (Count_e - 1) mod Cntr_Modulus;
end if;
end if;
end process test_eq;

-- aggregate makes trouble in Active HDL
(Carry_Out_a, nxt_cnt_a) <= RESIZE(Count_a, nxt_cnt_a\'length + 1) - 1;

test_ag: process (Clk) is
begin
if rising_edge(Clk) then
Test_Out_a <= Carry_Out_a;
if (Cnt_En OR not Carry_Out_a) then
Count_a <= nxt_cnt_a;
end if;
end if;
end process test_ag;


Down_Cntr is a procedure to hide the details of setting the new values of the counter and carry. I\'ll spare you the boring details.

The prior version of the Gowin tools produced some real spaghetti code of a design with multiple adder circuits.. or so I think. It was hard to tell what was what looking at a text net list with all the net renaming. Anyway, the latest version of the tools, 1.9.7beta seems to do an ok job. I see there is a Gowin® EDA_Gowin V1.9.7Beta_win and a Gowin_V1.9.7Beta_GowinSynthesis-only_win. I guess the one doesn\'t include the Synopsis tool. It seems to require a separate license, so not much good without that. I wonder if they give that out without a fee like Lattice does?

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209
 
On 18/10/2020 21:56, Rick C wrote:
On Sunday, October 18, 2020 at 10:28:20 AM UTC-4, Michael Kellett
wrote:
On 17/10/2020 22:11, Rick C wrote:
I\'ve nothing against Verilog, I\'ve been meaning to learn it for
years now, but just never got my focus on the task. I\'m working
with the Gowin devices and decided to try synthesis to see just
how some of my constructs are going to be generated. The native
Gowin synthesis tool doesn\'t seem to support VHDL. Either that
or they give some very strange error messages.

Info (EXT0100) : Run analyzation & elaboration Error
(EXT3044) : Analyze: cannot read format vhdl in this product
Error (EXT3044) : Analyze: cannot read format vhdl in this
product

Is analyzation even a word? It gets less than 1 million hits in
Google while Analysis gets 2.5 BILLION. I guess it is a work,
just not one people use much.

Anyway... the tool will invoke the Synplify tool, but I don\'t
seem to have a license at the moment. I\'ve sent an email about
this to the FAE contact. I should hear something by Monday. I\'m
a bit disappointed in that no one mentioned this even with having
asked questions about VHDL coding styles. I would have expected
someone to say, \"Yeah, that will infer what you are looking
for... but not with our tools. You\'ll have to spend a couple of
kilobucks for your own copy of Synopsis tools.\"

If I need to convert my code from VHDL to Verilog, I\'m going to
need a lot of hand holding. My main areas of concern is in
knowing about the various assumptions the tool makes when doing
arithmetic operations and test benches. I\'ve asked before about
good books to help a guy out. The frequent reply is none seem to
hit all the bases.

I used Verilog about 20 years ago and test benches were rather
awkward to say the least. I\'m sure they\'ve improved, but I think
that\'s going to be a bit of a learning curve.

Well, I guess I\'ll cross that bridge once I come to it.
Hopefully there will be good news on Monday.

The Gowin synthesis tool works on VHDL for me. If you want to email
me at mk@mkesc I\'ll send you a Dropbox link. Add .co.uk to the
other bit of the address.

MK

Thanks for your reply.

I figured it out. I was using a version from some months ago. VHDL
was just added recently. Now I was trying to examine the efficiency
of synthesis with code to obtain the carry out of a down counter to
allow it to be stopped at zero as you might want in a timing circuit
or a state machine. I couldn\'t find a way to visualize a schematic
for the results of synthesis. Turns out I still didn\'t have the most
recent version, 1.9.7beta which does have the schematic viewer.

Now I just need a way to change the colors in the schematic. They
use a neon cyan color for nets that is very hard to see. They also
use such a small font on the connection labels that I have to zoom in
so much to read them, I can\'t see the schematic with any perspective.
It\'s better than reading the durn net list, but not by a lot.

The results of the survey are...

Everyone (Lattice, Synplify Pro for Lattice and Gowin) gets the same
results after I got it all working. Three designs give a register
and adder for each bit in the counter plus one for the carry. The
fourth approach generates some extra logic to detect the current
value of the counter being zero directly using LUTs.

The approach that requires the least amount of code without producing
the extra logic requires an assignment to an aggregate which the
ActiveHDL simulator barfs on at run time with a strange complaint
about mismatched indices. If it were a true mismatch I would expect
the error to be flagged before the code is run. So maybe this is an
Aldec error.

constant Cntr_Width : positive := 13; constant Cntr_Modulus :
positive := 2**Cntr_Width; signal Count, nxt_cnt :
unsigned(Cntr_Width - 1 downto 0) := (others => \'0\'); signal Count_a,
nxt_cnt_a : unsigned(Cntr_Width - 1 downto 0) := (others => \'0\');
signal Count_e, nxt_cnt_e : natural range 0 to (Cntr_Modulus - 1) :=
0; begin

Down_Cntr (Count, nxt_cnt, Carry_Out);

test_sig: process (Clk) is begin if rising_edge(Clk) then Test_Out <=
Carry_Out; if (Cnt_En OR not Carry_Out) then Count <= nxt_cnt; end
if; end if; end process test_sig;

Carry_Out_e <= \'1\' when Count_e = 0 else \'0\'; -- produces an N wide
OR

test_eq: process (Clk) is begin if rising_edge(Clk) then Test_Out_e
= Carry_Out_e; if (Cnt_En OR not Carry_Out_e) then Count_e <=
(Count_e - 1) mod Cntr_Modulus; end if; end if; end process test_eq;

-- aggregate makes trouble in Active HDL (Carry_Out_a, nxt_cnt_a) <=
RESIZE(Count_a, nxt_cnt_a\'length + 1) - 1;

test_ag: process (Clk) is begin if rising_edge(Clk) then Test_Out_a
= Carry_Out_a; if (Cnt_En OR not Carry_Out_a) then Count_a <=
nxt_cnt_a; end if; end if; end process test_ag;


Down_Cntr is a procedure to hide the details of setting the new
values of the counter and carry. I\'ll spare you the boring details.

The prior version of the Gowin tools produced some real spaghetti
code of a design with multiple adder circuits.. or so I think. It
was hard to tell what was what looking at a text net list with all
the net renaming. Anyway, the latest version of the tools, 1.9.7beta
seems to do an ok job. I see there is a Gowin® EDA_Gowin
V1.9.7Beta_win and a Gowin_V1.9.7Beta_GowinSynthesis-only_win. I
guess the one doesn\'t include the Synopsis tool. It seems to require
a separate license, so not much good without that. I wonder if they
give that out without a fee like Lattice does?
Click to expand...

We seem to have drifted into discussing VHDL in the Verilog newsgroup.
Better than politics !

RESIZE did the same for me,

so I did this which seems to work.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;

entity rick_counter is
port(
Clk : in STD_LOGIC;
Cnt_en : in STD_LOGIC;
Test_out_a : out STD_LOGIC
);
end rick_counter;


architecture rick_counter of rick_counter is

constant Cntr_Width : positive := 13;
constant Cntr_Modulus : positive := 2**Cntr_Width;
signal Count_a, nxt_cnt_a : unsigned(Cntr_Width - 1 downto 0) := (others
=> \'0\');
signal Carry_Out_a : unsigned(0 downto 0) := \"0\";


begin

test_ag: process (Clk) is
begin
if rising_edge(Clk) then
--(Carry_Out_a, nxt_cnt_a) <= (RESIZE(Count_a, nxt_cnt_a\'length +
1)) - 1;
(Carry_Out_a, nxt_cnt_a) <= (Carry_Out_a & Count_a) - 1;
Test_Out_a <= std_logic(Carry_Out_a(0));
if (Cnt_En = \'1\' or Carry_Out_a = \"1\") then
Count_a <= nxt_cnt_a;
end if;
end if;
end process test_ag;

end rick_counter;

Sorry about the line wrapping.

MK
 
On Monday, October 19, 2020 at 5:58:51 AM UTC-4, Michael Kellett wrote:
On 18/10/2020 21:56, Rick C wrote:
On Sunday, October 18, 2020 at 10:28:20 AM UTC-4, Michael Kellett
wrote:
On 17/10/2020 22:11, Rick C wrote:
I\'ve nothing against Verilog, I\'ve been meaning to learn it for
years now, but just never got my focus on the task. I\'m working
with the Gowin devices and decided to try synthesis to see just
how some of my constructs are going to be generated. The native
Gowin synthesis tool doesn\'t seem to support VHDL. Either that
or they give some very strange error messages.

Info (EXT0100) : Run analyzation & elaboration Error
(EXT3044) : Analyze: cannot read format vhdl in this product
Error (EXT3044) : Analyze: cannot read format vhdl in this
product

Is analyzation even a word? It gets less than 1 million hits in
Google while Analysis gets 2.5 BILLION. I guess it is a work,
just not one people use much.

Anyway... the tool will invoke the Synplify tool, but I don\'t
seem to have a license at the moment. I\'ve sent an email about
this to the FAE contact. I should hear something by Monday. I\'m
a bit disappointed in that no one mentioned this even with having
asked questions about VHDL coding styles. I would have expected
someone to say, \"Yeah, that will infer what you are looking
for... but not with our tools. You\'ll have to spend a couple of
kilobucks for your own copy of Synopsis tools.\"

If I need to convert my code from VHDL to Verilog, I\'m going to
need a lot of hand holding. My main areas of concern is in
knowing about the various assumptions the tool makes when doing
arithmetic operations and test benches. I\'ve asked before about
good books to help a guy out. The frequent reply is none seem to
hit all the bases.

I used Verilog about 20 years ago and test benches were rather
awkward to say the least. I\'m sure they\'ve improved, but I think
that\'s going to be a bit of a learning curve.

Well, I guess I\'ll cross that bridge once I come to it.
Hopefully there will be good news on Monday.

The Gowin synthesis tool works on VHDL for me. If you want to email
me at mk@mkesc I\'ll send you a Dropbox link. Add .co.uk to the
other bit of the address.

MK

Thanks for your reply.

I figured it out. I was using a version from some months ago. VHDL
was just added recently. Now I was trying to examine the efficiency
of synthesis with code to obtain the carry out of a down counter to
allow it to be stopped at zero as you might want in a timing circuit
or a state machine. I couldn\'t find a way to visualize a schematic
for the results of synthesis. Turns out I still didn\'t have the most
recent version, 1.9.7beta which does have the schematic viewer.

Now I just need a way to change the colors in the schematic. They
use a neon cyan color for nets that is very hard to see. They also
use such a small font on the connection labels that I have to zoom in
so much to read them, I can\'t see the schematic with any perspective.
It\'s better than reading the durn net list, but not by a lot.

The results of the survey are...

Everyone (Lattice, Synplify Pro for Lattice and Gowin) gets the same
results after I got it all working. Three designs give a register
and adder for each bit in the counter plus one for the carry. The
fourth approach generates some extra logic to detect the current
value of the counter being zero directly using LUTs.

The approach that requires the least amount of code without producing
the extra logic requires an assignment to an aggregate which the
ActiveHDL simulator barfs on at run time with a strange complaint
about mismatched indices. If it were a true mismatch I would expect
the error to be flagged before the code is run. So maybe this is an
Aldec error.

constant Cntr_Width : positive := 13; constant Cntr_Modulus :
positive := 2**Cntr_Width; signal Count, nxt_cnt :
unsigned(Cntr_Width - 1 downto 0) := (others => \'0\'); signal Count_a,
nxt_cnt_a : unsigned(Cntr_Width - 1 downto 0) := (others => \'0\');
signal Count_e, nxt_cnt_e : natural range 0 to (Cntr_Modulus - 1) :> > 0; begin

Down_Cntr (Count, nxt_cnt, Carry_Out);

test_sig: process (Clk) is begin if rising_edge(Clk) then Test_Out <> > Carry_Out; if (Cnt_En OR not Carry_Out) then Count <= nxt_cnt; end
if; end if; end process test_sig;

Carry_Out_e <= \'1\' when Count_e = 0 else \'0\'; -- produces an N wide
OR

test_eq: process (Clk) is begin if rising_edge(Clk) then Test_Out_e
= Carry_Out_e; if (Cnt_En OR not Carry_Out_e) then Count_e <> > (Count_e - 1) mod Cntr_Modulus; end if; end if; end process test_eq;

-- aggregate makes trouble in Active HDL (Carry_Out_a, nxt_cnt_a) <> > RESIZE(Count_a, nxt_cnt_a\'length + 1) - 1;

test_ag: process (Clk) is begin if rising_edge(Clk) then Test_Out_a
= Carry_Out_a; if (Cnt_En OR not Carry_Out_a) then Count_a <> > nxt_cnt_a; end if; end if; end process test_ag;


Down_Cntr is a procedure to hide the details of setting the new
values of the counter and carry. I\'ll spare you the boring details.

The prior version of the Gowin tools produced some real spaghetti
code of a design with multiple adder circuits.. or so I think. It
was hard to tell what was what looking at a text net list with all
the net renaming. Anyway, the latest version of the tools, 1.9.7beta
seems to do an ok job. I see there is a Gowin® EDA_Gowin
V1.9.7Beta_win and a Gowin_V1.9.7Beta_GowinSynthesis-only_win. I
guess the one doesn\'t include the Synopsis tool. It seems to require
a separate license, so not much good without that. I wonder if they
give that out without a fee like Lattice does?


We seem to have drifted into discussing VHDL in the Verilog newsgroup.
Better than politics !

RESIZE did the same for me,

so I did this which seems to work.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;

entity rick_counter is
port(
Clk : in STD_LOGIC;
Cnt_en : in STD_LOGIC;
Test_out_a : out STD_LOGIC
);
end rick_counter;


architecture rick_counter of rick_counter is

constant Cntr_Width : positive := 13;
constant Cntr_Modulus : positive := 2**Cntr_Width;
signal Count_a, nxt_cnt_a : unsigned(Cntr_Width - 1 downto 0) := (others
=> \'0\');
signal Carry_Out_a : unsigned(0 downto 0) := \"0\";


begin

test_ag: process (Clk) is
begin
if rising_edge(Clk) then
--(Carry_Out_a, nxt_cnt_a) <= (RESIZE(Count_a, nxt_cnt_a\'length +
1)) - 1;
(Carry_Out_a, nxt_cnt_a) <= (Carry_Out_a & Count_a) - 1;
Test_Out_a <= std_logic(Carry_Out_a(0));
if (Cnt_En = \'1\' or Carry_Out_a = \"1\") then
Count_a <= nxt_cnt_a;
end if;
end if;
end process test_ag;

end rick_counter;

Sorry about the line wrapping.

MK
Click to expand...

Durned if that didn\'t work!!! When I looked at the right side it seemed pretty perfect. I know there can be issues where the right side doesn\'t match the left because the right side can be a range of sizes and can\'t choose one because the left side is ambiguous. But there\'s nothing ambiguous about the left side in this case. The right side should be a fixed size as set by the parameter to RESIZE. So more tests...

Using a concatenation works. So does changing the integer 1 to an unsigned literal, constant actually to make sure it was typed correctly.

constant One_uns : unsigned(Cntr_Width downto 0) := \"000000001\";
(Carry_Out_a, nxt_cnt_a) <= RESIZE(Count_a, nxt_cnt_a\'length + 1) - One_uns;

So the RESIZE is not to blame, rather the add/subtract operator? Looking that up the length of the sum/difference is always defined by the length of the operands. So this has to be a bug in Active-HDL that is triggered by this particular usage.

Let me say something about your code because it hits on the reason why I am doing this test. I\'m looking for a flag of the terminal count of various counters, i.e. the carry out. This has to be a combinational output, not a registered output. Making it a registered output means it doesn\'t appear until the next cycle so it can\'t be used to stop the counter.

I\'ve never done it before in the past, but I\'m really getting tired of the verbosity of VHDL and was trying to keep this simple structure lean. I would also like to apply standard software techniques of limiting scope of variables, mostly so an entity does not have a bazillion lines in the declaration section. Using variables puts the declaration right where they are used.

So I\'m not able to find a way to do any of this with this counter. If the register is in the clocked process there is no way to break out the combinational circuit feeding the counter (specifically the carry) without duplicating the entire adder circuit. This design was as good as I could get. There will be other logic in the counter process, so it isn\'t a total waste, but sometimes it is just so hard to write good code without feeling like I\'m writing the great American novel.

This design is going to use a lot of timing counters, hence my desire to make them efficient and code effective. Even using procedures doesn\'t really help because you still can\'t mix the registered and combinational outputs. It seems like there should be a way to extract a signal from the variables in a clocked process without creating two processes.

I guess this is a bit too much VHDL for a Verilog group. I did make a post in the VHDL group and no one responded.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209
 
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