LUT and Registers in Xilinx Virtex 2

[Julien Eyries]

Hello all,

I have one question about usage of LUT and Registers in Xilinx
Virtex 2 FPGA:

if, inside a slice, the LUT is consumed by some logic product, but
not the corresponding register, is this register available for other use
(for example, registering signal coming from an other slice) ? or is it
disabled for the whole design ? does it depend on the compilation tool ?

thanks,
Julien Eyries

 

[Allan Herriman]

On Mon, 22 Sep 2003 21:54:16 +0000, Julien Eyries
<NOeyries.SPAMjulien@wanadooPLEASE.fr> wrote:

Hello all,

I have one question about usage of LUT and Registers in Xilinx
Virtex 2 FPGA:

if, inside a slice, the LUT is consumed by some logic product, but
not the corresponding register, is this register available for other use
(for example, registering signal coming from an other slice) ? or is it
disabled for the whole design ? does it depend on the compilation tool ?

It is available for other purposes. Look at the picture of the
internals of a slice in the V2 data sheet.

If you are using less than 99% of the slices in the FPGA, map (which
is responsible for assigning logic to slices) will not put unrelated
LUTs and FFs into the same slice.
(See the map report for the amount of "unrelated logic packing".)
This explains why you can keep adding logic to your design, but the
slice utilisation stays at 99%.
Map tries to avoid unrelated logic packing because this tends to make
the later placement pass much more difficult.

Does this waste slices? Sure, but what else are you going to do with
them?

Regards,
Allan.