Local Controller for latch

[Mohd Zulkarnain Jaranee]

Hi, I want to make a controller which will enable the latch.

As you can seen on my code below, the signal en will take the output from w AND x to enable the latch. After that, w and x will fetch the en. For example, initially, let say the w and x values start at 1, the en will become 1 and cause the latch to fetch data from data_in to data_out. After that, en will become the input of w and x and cause the latch to disable. However, the circuit didn't work when I tested it using altera university waveform program. The data_out didnt take the value of data_in. I can't figure out what is the problem still I'm new in VHDL. Hope you can assist/advice me on this Sorry for my bad english.

library ieee;
use ieee.std_logic_1164.all;
entity gasp_ctrl is
port(
w,x : inout std_logic; --! bidirectional wire
data_in : in std_logic; --! Data In when latch is enable
data_out: out std_logic --
);
end gasp_ctrl;

architecture ctrl of gasp_ctrl is
signal en, ww, xx : std_logic;

begin
en <= w and x; ------
ww <= en;
xx <= not en;
w <= ww;
x <= xx;


-------- Latch ------
process(en)
begin
if(en = '1') then
data_out <= data_in;
end if;
end process;
end gasp_ctrl;

 

[rickman]

On 12/2/2014 3:30 AM, Mohd Zulkarnain Jaranee wrote:

Hi, I want to make a controller which will enable the latch.

As you can seen on my code below, the signal en will take the output from w AND x to enable the latch. After that, w and x will fetch the en. For example, initially, let say the w and x values start at 1, the en will become 1 and cause the latch to fetch data from data_in to data_out. After that, en will become the input of w and x and cause the latch to disable. However, the circuit didn't work when I tested it using altera university waveform program. The data_out didnt take the value of data_in. I can't figure out what is the problem still I'm new in VHDL. Hope you can assist/advice me on this Sorry for my bad english.

library ieee;
use ieee.std_logic_1164.all;
entity gasp_ctrl is
port(
w,x : inout std_logic; --! bidirectional wire
data_in : in std_logic; --! Data In when latch is enable
data_out: out std_logic --
);
end gasp_ctrl;

architecture ctrl of gasp_ctrl is
signal en, ww, xx : std_logic;

begin
en <= w and x; ------
ww <= en;
xx <= not en;
w <= ww;
x <= xx;


-------- Latch ------
process(en)
begin
if(en = '1') then
data_out <= data_in;
end if;
end process;
end gasp_ctrl;

You have some fundamental misunderstandings of how logic and HTML work.
I can identify two errors without trying.

The really big one is that you seem to want X and W to be inputs, but
also assign them in your code. Which are they, internal signals or
inputs? Defining them as inout in your port doesn't make this
synthesizeable.

The next error is creating a feedback loop in the concurrent statements.
By assigning values to X and W that depend on X and W you are creating
unintentional latches.

Do this. This is a simple circuit. Try drawing a logic schematic of
what you think this should produce in the FPGA. Use AND and NOT
functions and show what it should be.

Finally, did you synthesize this or just load it into a chip and try
running it? I'm surprised the tools didn't complain about this code. I
guess maybe it just gave you warnings which you didn't pay attention to.

Oh, there's a third error. You need to add data_in to your sensitivity
list in the process... I don't think the simulation will work correctly
without it.

--

Rick