V
valtih1978
Guest
Now, what does the fact that value is the same as quadrupled '"'
character tell to us? What should the input bit_string_literal look like?
Section 15.8, says "For a character in the simplified value that is not
interpreted as an extended digit, each character in the replacement
sequence
is the same as the character replaced."
So if you run across a " or a "" in the input, it should be copied over as-is
into the output unchanged.
And now my question again: what should user input look like? I can copy
over '-' to get "----" in the resulting string literal value. What
should user enter to get '"' instead of '-'? Saying 'copy, as-is' means
that user should enter single "-mark in the bit vector literal instead
of -mark, right? Or what? Meantime you say that they need to be
duplicated to circumvent the BNF grammar.
Since a " would end up not being a legal bit value when you're all done
converting and an error is going to be flagged anyway, I would think
a compiler could stop and flag the error at that point.
I have heard that several times already and never received the answer
"why illegal". Who says 'illegal'? Why '-' is legal but '"' is illegal?
Should I constrain legal bit string values to those used in bit or
std_logic? My impression always was that user can define its own logic
values and use whatever characters are legal in the enumeration. Why is
'"' illegal? Is my convincing wrong?
Moreover, you say that bit vector has the same values as string_literal.
Does it mean that '"' is illegal in the string_literal?
I do not think that you can treat it equally with the issues that I have
raised.
Right, only things that you bring up are important. Gotcha.
First, this is a fascism. It is a fascism to say that "we are right
because these are we". Secondly, this is your position. You say LRM
creates a problem because your tool had a bug. But it is not, as we
explained. Third, you say that this is mine position, despite I discuss
the LRM rather than a bug in your tool. I have explained why there is no
problem with negatives. You should point to a flaw in my logic rather
than say that I must buy whatever you say or I am a unconscious bastard.
The double quote and physical unit is simply unparsable.
Well, other tools I assume are able to parse it, although I admit I
haven't bothered to try to insert a " into a bit string to see what
happens.
I have even looked in source code of such a tool. Why am I still here?
Yestuday, I have discovered one more conflict of this kind.
function_call ::= name [(args)]
How do you distinguish it from a simple identifier if arguments are not
specified?
In your example, 'name' will be the name of the function that has
already been defined previously in the source code as a function with
no arguments. The vocabulary keeps expanding as source code is
processed.
It starts with only the keywords, then adds on everything else that gets
declared. Not sure why you see any issue here.
Because "vocabulary" is the collection of scopes that you get during
elaboration, which seems to be a step supposed to happen after the parse
has finished. Meantime, VHDL seems to be context-sensitive language and
cannot parse without elaborating immediately. That is to parse a(b),
your parser must beware that a is a type or a function to choose a
corresponding grammar production, whether it should be a type conversion
or array indexing or function call. There should be elaborated model to
tell you that.
At the same time, LRM presents material as if elaboration is a thrid
step following 1) parsing and 2) analysis. All tools that I have used
perpetuate this approach when propose you to select the top level for
elaboration after parsing completed. The dilemma "to combine elaboration
with parsing or elaborate afterwards" leaves me very puzzled. Your hints
suggest that I must combine the two.