Learning VHDL beyond basics

a month ago I decided that I was lacking FPGA knowhow, said and done I ordered an experiment board (beeing an opensource aficionado I ordered the LogicStart MegaWing bundle with a Papilio One 500k) and two books, Ashenden's "The Designers Guid to VHDL" and Pong Chu's "FPGA Prototyping by VHDL Examples: Spartan 3". My reasoning behind these two books is that I start with Ashenden to learn the whole language then go to Pong to learn how to write syntezisable VHDL, since both contain exercises they make for really good self teaching material. I know Pong is targeting another experiment board but it's the same FPGA and im very confident I can myself make adjustments, except for e.g. the PS2 port which my papilio thankfully does not have.

I have now started to search for what to do after these books, how do I get more advanced in my FPGA knowledge. I'm a software guy and if I got the question "I want to start programming" from someone new to programming I would recomend a good starting book in python, then a good book on how to do test driven design, then a book about patterns, then moving to C followed by a book about object oriented design, then perhaps going for a best practice book and so on, by level of complexity and relevance. I have scoured the internet (or feels like it) to find such a list regarding FPGA, but at no luck so far, so thinking of posting the question here.

I have looked at three books for continued learning after I'm finished with Pong

Volnei Pedroni: Circuit Design and Simulation with VHDL ; seems to be aimed at explaining deeper the differences beetwen syntezisable and simulated VHDL. Though it seem to go through the VHDL language constructs yet again perhaps it is too much overlapping with Pong and Ashenden

Volnei Pedroni: Finite State Machines in Hardware: Theory and Design ; seems a good continuation, I understand that FSM is a very important topic in HW world and that they are completely different from SW FSM, also it seem to have excersises after each chapter which is good.

Pong Chu - RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability ; seems good, no more comments.

Thats my thinking, any suggestions or comments? Have not come about any books regarding FPGA testing? Perhaps I should look outside the more hands on book to one of the "meta" books out there?

 

[Lars Asplund]

If you have a software and TDD background I would recommend a look at VUnit, an open-source unit testing framework for VHDL, which we just released on GitHub (https://github.com/LarsAsplund/vunit). It will let you work with TDD in a way that you are used to.

I'm just about to add more introduction material on YouTube so make sure to follow the project and sign up for the referenced YouTube channel if you're interested.

Lars

 

[KKoorndyk]

The Ashenden book is a great reference but may be a bit difficult to sit and read cover to cover to learn the language. I assume you bought the 3rd edition, right? A lot of examples early in the book are fine for models and learning the language, but are not synthesizable. Pay particular attention to the new Design for Synthesis chapter (21).

Along the lines of rickman's suggestion, I would *HIGHLY* recommend that you read the synthesis guides for Altera Quartus II and Xilinx's XST and Vivado Synthesis. They'll provide guidance on what constructs are supported.
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-vivado-synthesis.pdf

I would also recommend reading Xilinx's UltraFast Design Methodology Guide. It is obviously heavily geared towards the Vivado tool suite, but it also contains a lot of best practices.
http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf

You might also consider an on-demand college course like the one mentioned on this page:
http://dangerousprototypes.com/2013/03/09/cornell-online-courses-designing-with-microcontrollers-and-fpgas/

Altera also offers quite a few free, on-demand training "courses", but they're a little light on quality content. Xilinx also has several videos:
http://www.xilinx.com/training/free-video-courses.htm#FPGA

Doulos has some good, free material on their site: http://www.doulos.com/knowhow/vhdl_designers_guide/

Check out OpenCores.org. There are a ton of open modules that you can learn from reviewing, but be careful - some are garbage.

There's also some material on the EETimes Programmable Logic Designline blog.

 

[Leonardo Capossio]

It is difficult to say, since advanced stuff this days is mostly done by experience and reading other peoples code/papers.

Also...remember that actually VHDL is a low level language, and what you actually have to get knowledge about is hardware architectures (or digital design in general). Get into some project, set some goal, when the need arises search for more specific knowledge.

There is possible exception, if you only want to do verification (usually attributed to be a pure-software task), then I would advise to get some verification book I don't know about, but I do know that if you are going to be using VHDL the most advanced verification can be done with OSVVM (search it). Otherwise SystemVerilog is what you are looking for. But advanced verification is most well suited to ASICs, in FPGA sometimes it doesn't make sens because you can prototype quickly.

I could recommend Altera Cookbook for learning a couple of synthesis tricks (search, it is free downloadable, but it is mostly in Verilog). Then for Digital Design I recommend Wakerly (Digital Design: Principles and Practices), it is one the most comprehensible and cool books that I have found (and also detailed). Also I recommend a The Design Warrior's Guide to FPGA, as a general FPGA knowledge book.

Good luck and welcome to the FPGA world!

 

[rickman]

On 1/9/2015 8:09 AM, johan.falkenstrom@gmail.com wrote:

a month ago I decided that I was lacking FPGA knowhow, said and done I ordered an experiment board (beeing an opensource aficionado I ordered the LogicStart MegaWing bundle with a Papilio One 500k) and two books, Ashenden's "The Designers Guid to VHDL" and Pong Chu's "FPGA Prototyping by VHDL Examples: Spartan 3". My reasoning behind these two books is that I start with Ashenden to learn the whole language then go to Pong to learn how to write syntezisable VHDL, since both contain exercises they make for really good self teaching material. I know Pong is targeting another experiment board but it's the same FPGA and im very confident I can myself make adjustments, except for e.g. the PS2 port which my papilio thankfully does not have.

I have now started to search for what to do after these books, how do I get more advanced in my FPGA knowledge. I'm a software guy and if I got the question "I want to start programming" from someone new to programming I would recomend a good starting book in python, then a good book on how to do test driven design, then a book about patterns, then moving to C followed by a book about object oriented design, then perhaps going for a best practice book and so on, by level of complexity and relevance. I have scoured the internet (or feels like it) to find such a list regarding FPGA, but at no luck so far, so thinking of posting the question here.

I have looked at three books for continued learning after I'm finished with Pong

Volnei Pedroni: Circuit Design and Simulation with VHDL ; seems to be aimed at explaining deeper the differences beetwen syntezisable and simulated VHDL. Though it seem to go through the VHDL language constructs yet again perhaps it is too much overlapping with Pong and Ashenden

Volnei Pedroni: Finite State Machines in Hardware: Theory and Design ; seems a good continuation, I understand that FSM is a very important topic in HW world and that they are completely different from SW FSM, also it seem to have excersises after each chapter which is good.

Pong Chu - RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability ; seems good, no more comments.

Thats my thinking, any suggestions or comments? Have not come about any books regarding FPGA testing? Perhaps I should look outside the more hands on book to one of the "meta" books out there?

I don't think I ever read HDL books to learn higher level ideas. I read
them to learn the basics. Oddly enough every one had a rather different
approach to teaching what I think is very simple and straightforward
really. Still, they got me over the hump and on the road to teaching
myself.

I learned FSMs in school and never felt the need to worry with how
others write FSM code. I also tossed most of what I learned about FSMs
actually. The whole Mealy/Moore thing is not so valuable when coding
them up in HDL. I don't think any of my FSM designs are purely either
now. It was a useful concept to learn about FSMs, but not so useful in
practice.

The Pong Chu book may be useful, at least it sounds good. I have to
wonder if it is better than reading the app notes from the FPGA vendors.
All HDL compilers are a little different and of course the chip
architectures are also different. So how can one book be applicable to
all? There is a standard for synthesis which I suppose is what he covers.

I suggest you look more toward the vendors for info on how to use their
tools. To me that is the bottom line. After all, in FPGAland there is
no way to completely avoid the vendor tools.

--

Rick

 

[Rob Gaddi]

On Fri, 9 Jan 2015 12:53:07 -0800 (PST)
KKoorndyk <kris.koorndyk@gmail.com> wrote:

The Ashenden book is a great reference but may be a bit difficult to sit and read cover to cover to learn the language. I assume you bought the 3rd edition, right? A lot of examples early in the book are fine for models and learning the language, but are not synthesizable. Pay particular attention to the new Design for Synthesis chapter (21).

Along the lines of rickman's suggestion, I would *HIGHLY* recommend that you read the synthesis guides for Altera Quartus II and Xilinx's XST and Vivado Synthesis. They'll provide guidance on what constructs are supported.
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-vivado-synthesis.pdf

Wow. Just flipped through the Vivado Synthesis guide. It's all still
recommending you use std_logic_arith/std_logic_unsigned. There's no
mention of numeric_std at all, let along the VHDL-2008 packages.

This is why we can't have nice things.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

 

[Rob Gaddi]

On Fri, 9 Jan 2015 15:22:03 -0800
Rob Gaddi <rgaddi@technologyhighland.invalid> wrote:

On Fri, 9 Jan 2015 12:53:07 -0800 (PST)
KKoorndyk <kris.koorndyk@gmail.com> wrote:

The Ashenden book is a great reference but may be a bit difficult to sit and read cover to cover to learn the language. I assume you bought the 3rd edition, right? A lot of examples early in the book are fine for models and learning the language, but are not synthesizable. Pay particular attention to the new Design for Synthesis chapter (21).

Along the lines of rickman's suggestion, I would *HIGHLY* recommend that you read the synthesis guides for Altera Quartus II and Xilinx's XST and Vivado Synthesis. They'll provide guidance on what constructs are supported.
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-vivado-synthesis.pdf


Wow. Just flipped through the Vivado Synthesis guide. It's all still
recommending you use std_logic_arith/std_logic_unsigned. There's no
mention of numeric_std at all, let along the VHDL-2008 packages.

This is why we can't have nice things.

Never mind. Finally made it all the way to the section on the IEEE
packages for VHDL, where they do mention support for numeric_std,
fixed_pkg, and float_pkg. The latter two are just shunted off into
ieee_proposed. Good to see support for such things, even if all their
design examples are still recommending packages that were deprecated in
1992.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

 

[KJ]

On Monday, January 12, 2015 at 5:31:48 AM UTC-5, Sean Durkin wrote:

I'd like to stick to std_ulogic in my designs, but it's a hassle to have
to convert to std_logic every time I connect to a core or code snippet
from them, sometimes needing intermediate signals just for the
conversion (because no type conversions allowed in instantiations...).
So in the end you can either have readable code or "safe" code.

No conversion is necessary between std_logic and std_ulogic; only between std_logic_vector and std_ulogic_vector. If your tools support VHDL-2008, you don't even need to convert the vectors. If your tools do not support VHDL-2008, you can put the type conversion right in the port map (both for inputs and outputs) so there is no need for intermediate signals.

Example: My_Entity port map(
std_logic_vector(some_slv) => some_sulv,
some_other_slv => std_ulogic_vector(some_other_sulv));

Kevin Jennings

 

[Sean Durkin]

Rob Gaddi wrote:

Wow. Just flipped through the Vivado Synthesis guide. It's all still
recommending you use std_logic_arith/std_logic_unsigned. There's no
mention of numeric_std at all, let along the VHDL-2008 packages.

This is why we can't have nice things.

Not only that, but all their examples and all of their cores use
std_logic and std_logic_vector almost exclusively, instead of
std_ulogic/std_ulogic_vector. That is not only useless, because the
hardware doesn't really support it (what does a FF do with an 'X'
input?), but more importantly it prevents detecting multiple driver
errors early in the process (like right at the beginning during VHDL
elaboration).
I'd like to stick to std_ulogic in my designs, but it's a hassle to have
to convert to std_logic every time I connect to a core or code snippet
from them, sometimes needing intermediate signals just for the
conversion (because no type conversions allowed in instantiations...).
So in the end you can either have readable code or "safe" code.

At the moment (at least up to Vivdao 2014.3) they have an issue in
Vivado that causes them sometimes to not detect multiple drivers at all;
but even if they do, you sometimes only get a "critical warning" that
does not stop the flow and can be easily missed when you don't search
the logs for it (or you can configure synthesis to promote that warning
to an error). The only time you really get a multiple drivers error is
at the very end during bitfile generation, so they let you waste hours
with a completely useless synthesis/map/pnr run before issuing an error
that should really occur before it starts synthesizing...

Greetings,
Sean

 

[Sean Durkin]

KJ wrote:

On Monday, January 12, 2015 at 5:31:48 AM UTC-5, Sean Durkin wrote:

I'd like to stick to std_ulogic in my designs, but it's a hassle to
have to convert to std_logic every time I connect to a core or code
snippet from them, sometimes needing intermediate signals just for
the conversion (because no type conversions allowed in
instantiations...). So in the end you can either have readable code
or "safe" code.

No conversion is necessary between std_logic and std_ulogic; only
between std_logic_vector and std_ulogic_vector.

Correct, but that only messes things up further: you need a conversion
for one signal and not for the other... Again, sucks for readability IMHO.

> If your tools support VHDL-2008, you don't even need to convert the vectors.
Well, Vivado has some very rudimentary support vor VHDL-2008, but not
for that AFAIK.

If your tools do not support VHDL-2008, you can put the type conversion
right in the port map (both for inputs and outputs) so there is no
need for intermediate signals.
Example: My_Entity port map(
std_logic_vector(some_slv) => some_sulv,
some_other_slv => std_ulogic_vector(some_other_sulv));

Ah, OK, didn't know about the type conversion of the port (the second
line in your example).
I only tried converting the actual, which does not work for entity
outputs (Vivado quits saying "output designator some_slv cannot contain
an actual type-conversion"). Now that you say it, kinda makes sense to
put the conversion at the "source", I just never had dared to use type
conversions on the ports themselves, only on signals connected to ports.

The entire std_ulogic-thing just seems to be utterly broken in Vivado.
Even if there wasn't added hassle for conversions, it wouldn't help any,
since Vivado synthesis doesn't catch multiple drivers in some cases,
which for me is the main reason to use std_ulogic in the first place.

Concurrent assignments like:

sig <= some_other_sig;
....
sig <= '0';

.... with "sig" being a std_ulogic do not produce an error; this produces
a bitfile that simply does not work as expected, no warnings or errors
in any of the logfiles. Modelsim or any other synthesis tool do not even
compile that, which is what I'd expect. Interesting enough, the
simulation tool that comes with Vivado does also not compile that, but
the synthesis tool by the same vendor integrated in the same IDE does
not seem to have a problem with it.

It took a lot of complaining and week-long discussions until Xilinx even
acknowledged that this is indeed a bug, and there's a CR for it now.
Don't know when it will be fixed... I haven't tried the latest Vivado
release though; it might be fixed now, but at least there's nothing in
the release notes about this issue being addressed. I'm in
release-freeze now and don't have half a day to spare to install and try
out the new release.

Anyway, to cut a long story short:
- Xilinx still use std_logic_arith in almost all of their code
- Xilinx still use std_logic in almost any case, even if std_ulogic
would make a lot more sense IMHO

Old habits really die hard...

 

[Andy]

VHDL-2008 redefines std_logic_vector as a resolved subtype of std_ulogic_vector, using a new syntax that effectively applies the scalar resolution function to each bit (meaning each bit is also resolved), so they are now interchangeable.

Whether or not multiple drivers are allowed is dependent on the type/subtype of the object being driven. So now, you can declare your signals/ports as SULV and connect to IP with SLV ports just fine, with no port conversions or any other syntactic gymnastics.

I do not know whether Xilinx Vivado supports this yet. If not, open a bug for it. This is how we get what we want. There are other (better) synthesis tools available (Synplify & Precision are two), and it doesn't hurt to remind Xilinx of that fact.

Andy

 

[Rob Gaddi]

On Thu, 15 Jan 2015 10:49:03 -0800 (PST)
Andy <jonesandy@comcast.net> wrote:

VHDL-2008 redefines std_logic_vector as a resolved subtype of std_ulogic_vector, using a new syntax that effectively applies the scalar resolution function to each bit (meaning each bit is also resolved), so they are now interchangeable.

Whether or not multiple drivers are allowed is dependent on the type/subtype of the object being driven. So now, you can declare your signals/ports as SULV and connect to IP with SLV ports just fine, with no port conversions or any other syntactic gymnastics.

I do not know whether Xilinx Vivado supports this yet. If not, open a bug for it. This is how we get what we want. There are other (better) synthesis tools available (Synplify & Precision are two), and it doesn't hurt to remind Xilinx of that fact.

Andy

The problem is that threat lacks credibility. Xilinx doesn't give a
damn whether you don't want to use their software to do synthesis so
long as you're going to buy their silicon to put it on. The software
is almost certainly a money loser, even with their preposterous and
short-sighted efforts to squeeze money out of you for the right to use
their chips.

Not that Altera's more than fractionally better, mind.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

 

[Sean Durkin]

Andy wrote:

I do not know whether Xilinx Vivado supports this yet. If not, open a
bug for it. This is how we get what we want. There are other (better)
synthesis tools available (Synplify & Precision are two), and it
doesn't hurt to remind Xilinx of that fact.

Well, it's getting increasingly difficult to open bugs. They used to
have this WebCase thing on their website you could use, but that is now
only available to premium customers. The rest has to go through the
Xilinx user support forums and/or through the FAE that is usually
totally swamped already.
And, as I said before, going through the forum for me resulted in
week-long discussions before they even ackowledged that there was indeed
a problem there (A SULV with multiple drivers should result in an error
no matter which VHDL standard is chosen...).

So if it's that hard to get them recognize something that very clearly
is a bug, how interested do you think they are in adding "nice to have"
features that the majority of FPGA developers still doesn't even know
about (sadly)?
AFAIK, the rudimentary VHDL-2008-support they do have was requested by
one of the big customers, the rest they don't really seem to care about...

 

[Andy]

Does anyone know that Vivado does not support this 2008 feature?

Or do we simply assume not, and accept it like sheep?

Vote with your next design-in.

Andy

 

[KKoorndyk]

On Tuesday, January 20, 2015 at 11:41:55 PM UTC-5, Andy wrote:

Does anyone know that Vivado does not support this 2008 feature?

Or do we simply assume not, and accept it like sheep?

Vote with your next design-in.

Andy

http://www.xilinx.com/support/answers/62005.html

The supported language constructs are as follows:

Feature Vivado Release
Unconstrained Element Types 2014.3
Relational operators: ??, ?=, ?/=, ?>, ?>=, ?<, ?<= 2014.3
Maximum and Minimum 2014.3
shift operators 2014.3
bit_vector, boolean_vector, integer_vector and the predefined operators 2014.3
Strength Reduction Functions 2014.3
Unary reduction Operators (and,or,nand,nor,xor,xnor) 2014.3
Array Logic Operators 2014.3
Scalar Logic Operators 2014.3
If-else-if & Case Generate 2014.3
Sequential Signal Assignments 2014.3
Matching Select for Variables 2014.3
Matching Case for Variables 2014.3
Matching Select for Signals 2014.3
Matching Case for Signals 2014.3
Case? Statement 2014.3
Select? Statement 2014.3
Slices in aggregates 2014.3
Sized Bit String Literals 2014.3
Reading Output Ports 2014.3
Expressions in Port Maps 2014.3
Process(all) 2014.3
Referencing Generics in Generic Lists 2014.3
Relaxed return rules for Function Return Values 2014.3
Relaxed Qualified Expressions 2014.3
Type Conversions 2014.3
Extensions to globally static and locally static expressions 2014.3
Static Ranges and Integer expressions in range bounds 2014.3
Block Comments 2014.3
std_logic_1164/Numeric_bit/Numeric_std updates 2014.3

 

On Friday, January 9, 2015 at 8:09:03 AM UTC-5, johan.fa...@gmail.com wrote:

a month ago I decided that I was lacking FPGA knowhow, said and done I ordered an experiment board (beeing an opensource aficionado I ordered the LogicStart MegaWing bundle with a Papilio One 500k) and two books, Ashenden's "The Designers Guid to VHDL" and Pong Chu's "FPGA Prototyping by VHDL Examples: Spartan 3". My reasoning behind these two books is that I start with Ashenden to learn the whole language then go to Pong to learn how to write syntezisable VHDL, since both contain exercises they make for really good self teaching material. I know Pong is targeting another experiment board but it's the same FPGA and im very confident I can myself make adjustments, except for e.g. the PS2 port which my papilio thankfully does not have.

I have now started to search for what to do after these books, how do I get more advanced in my FPGA knowledge. I'm a software guy and if I got the question "I want to start programming" from someone new to programming I would recomend a good starting book in python, then a good book on how to do test driven design, then a book about patterns, then moving to C followed by a book about object oriented design, then perhaps going for a best practice book and so on, by level of complexity and relevance. I have scoured the internet (or feels like it) to find such a list regarding FPGA, but at no luck so far, so thinking of posting the question here.

I have looked at three books for continued learning after I'm finished with Pong

Volnei Pedroni: Circuit Design and Simulation with VHDL ; seems to be aimed at explaining deeper the differences beetwen syntezisable and simulated VHDL. Though it seem to go through the VHDL language constructs yet again perhaps it is too much overlapping with Pong and Ashenden

Volnei Pedroni: Finite State Machines in Hardware: Theory and Design ; seems a good continuation, I understand that FSM is a very important topic in HW world and that they are completely different from SW FSM, also it seem to have excersises after each chapter which is good.

Pong Chu - RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability ; seems good, no more comments.

Thats my thinking, any suggestions or comments? Have not come about any books regarding FPGA testing? Perhaps I should look outside the more hands on book to one of the "meta" books out there?

Want to learn more in engineering? If you are interested in learning
VHDL programming and FPGA development take my course today! This coupon
is good till April 6th, 2015 for $60 - 40% off the cost of the class at
regular price! Join now!
https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=March60#/

 

Hi, if you or anyone you know is interested in training or need additional learning material for VHDL and FPGA programming check out my course! I'm offering a special for $10 with lifetime access!! This coupon is valid till 4/7/15!
www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=VHDL10#/

 

[Derek Simmons]

If somebody tells me that they are going to school to become a doctor, I congratulate tham and ask them if they have an area of interest. You haven't told us what or area of interest or what you intend on using it for. So, in the vein of a column in my favorite guitar magazine titled, "What strings do you use?," I have answered,"What VHDL and computer design books are on your bookshelf."

There are a lot of books here but I have gotten rid of a lot more and these are the ones I've held onto.

VHDL LANGUAGE TEXTS

Pong P. Chu, "RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability," ISBN: 0-471-72092-5. This is my preferred text at the moment but the big sore spot is its price tag. The information is up to date. I really liked the chapters Register Transfer Methodology and I found them invaluable in implementing a vector-matrice math processor. [NOTE: At one time somebody announced in this group the public release of a library of vector and matrice primitives. Sure enough, somebody grab the library and did a literal implementation of their algorithm. They came back and bashed the library because they ran out of resources. If I was their boss I would be embarassed and considered sending them on an unpaid sabbatical to learn VHDL and resource sharing.]

Peter J. Ashenden, "The designer's Guide to VHDL," ISBN: 1-55860-270-4. This the text I really learned VHDL from. I made two passes at reading and doing the exercises. The exercises in the text are given a difficulty level of 1 to 4. On the first pass I did the problems with difficulty rating of 1 to 3. On the second pass I created test benches to demonstrate the solutions and I did the level 4 problems. My favorite problem to talk about is at the end of Chapter 14, "Generate Statements", problem 14. The problem ask you to create a hypercube multicomputer. The solution allows you to paramterize the number of nodes. Each node is made up of a router and a processing element. The router would pass a packet from a node to its destination node following a specific set of rules. When it reached its destination the processor I created would create a new destination node. My test bench showed that it could systematically pass the packet to each node. Then I should each node could route a packet from one node to each of the others. And, finally I showed it could route using each of the links between nodes. It makes for interesting discussions at job interviews.

Sundar Rajan, "Essential VHDL: RTL Synthesis Done Right," ISBN:0-9669590-0-0. This book is a fast pace introduction to VHDL and really interesting examples. I would recommend this to somebody that is faced with a small to medium size project but also would recommend that they have a copy of CHU's or ASHENDEN's for a more indepth coverage of material.

Peter Wilson, "Design Recipes for FPGAs," ISBN: 978-0-7506-6845-3. I wouldn't say they are good examples but I found it useful in solving writers block. Nothing is more frustrating then trying to do something and you can see the solution in your head but can connect it with how to implement it. Sometimes paging through this I see something related or even unrelated then all the peices of the problem I'm trying to solve fall into place.

Douglas J. Smith, "HDL Chip Design: A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDl or Verilog," ISBN: 0-9651934-3-8. I include this only as an honorable mention because it was a highly respected text but as VHDL as evolved it has become dated. Some engineers still cling to it. If somebody referes to the blue book or a blue book, this is the book they referring to. If you can borrow a copy its worth looking through. I keep my copy because the typography, layout and organization make it easy to read.


ADVANCED VHDL TEXTS

Steve Kilts, "Advanced FPGA Design: Architecture, Implementation, and Optimization," ISBN: 970-0-470-05437-6. An advance practices text. It guides the reader through solving more difficult design issues that are more system related then VHDL related.

Jean-Pierre Deschamps, Géry Jean Antoine Bioul and Gustavo D. Sutter, "Synthesis of Arithemtaic Circuits: FPGA, ASIC, and Embedded Systems," ISBN: 0-471-68783-9. The problems I'm normally faced with are math oriented or heavily math dependent. There is VHDL code on the author's website for the examples in the text.

Charles H. Roth, Jr., "Digital Systems Design Using VHDL," ISBN: 0-534-95099-X. This book is dated. It was from the period of when PCs had 486's for processors. I liked the examples and exercises. I don't recommend it but if you find a copy I think its worth your time to page through to see if anything sparks your interest. The reason I keep it is because it has design examples for UART and floating point multiplier.


OTHER

Clive "Max" Maxfield, "The Design Warrior's Guide to FPGA's: Devices, Tools and Flows," ISBN: 0-7506-7604-3. If you are working in industry or a student you should read this at least once. If you take to heart the topics it covers will give your work the WOW factor. When you are writing your design and engineering documents and you're 2/3 of the way through it, page through this book to see if you are missing anything or you can add something more. If you do that, someday somebody is going to say "Wow, I didn't think of that!" It talks about all that other stuff that isn't part of coding but is just as important, like design flow, reusability, intellectual property, ect.

Wim Vanderbauwhede and Khaled Benkrid, "High-Performance Computing Using FPGAs," ISBN: 978-1-4614-1790-3. My area of interest is in accelerating applications. So, this book would be of particular interest for my objectives.


COMPUTER ARCHITECTURE

Kai Hwang, "Advanced Computer Architecture: Parallelism, Scalability, Programmability," ISBN: 0-07-031622-8. This is a basic computer architecture book. As architects study buildings and arcitecture I think more of an emphasis should be given to studying computer systems and computer architecture.

Kai Hwang, "Computer Arithmetic: Principles, Architecture, and Design," ISBN: 0-471-03496-7. This book has case studies on how arithematic functions and pipelines were implemented in computer systems when both processor and memory were expensive. I didn't copy it but reading the sections on the TI ASC gave me my eureka moment for my vector-matrice processor. The TI ASC had a scalable SIMD architecture. It could be purchased with 1 to 4 math pipes..

Kai Hwang and Fayé A. Briggs, "Computer Architecture and Parallel Processing," ISBN: 0-07-031556-6. Were as Hwang's first text was a first semester text this would be the second semester text for a course study in computer design and architecture. This book describes the processor architecture of parallel processors and super computers. More information on the TI ASC and CDC Star-100.

Israel Koren, "Computer Arithmetic Algorithms," ISBN: 1-56881-160-8. The 20 years apart that this book was published from Kai's there isn't a big difference in material and it makes you wonder is Kai was a head of his time or has so little really changed.

 

On Friday, January 9, 2015 at 3:09:03 PM UTC+2, johan.fa...@gmail.com wrote:

a month ago I decided that I was lacking FPGA knowhow, said and done I ordered an experiment board (beeing an opensource aficionado I ordered the LogicStart MegaWing bundle with a Papilio One 500k) and two books, Ashenden's "The Designers Guid to VHDL" and Pong Chu's "FPGA Prototyping by VHDL Examples: Spartan 3". My reasoning behind these two books is that I start with Ashenden to learn the whole language then go to Pong to learn how to write syntezisable VHDL, since both contain exercises they make for really good self teaching material. I know Pong is targeting another experiment board but it's the same FPGA and im very confident I can myself make adjustments, except for e.g. the PS2 port which my papilio thankfully does not have.

I have now started to search for what to do after these books, how do I get more advanced in my FPGA knowledge. I'm a software guy and if I got the question "I want to start programming" from someone new to programming I would recomend a good starting book in python, then a good book on how to do test driven design, then a book about patterns, then moving to C followed by a book about object oriented design, then perhaps going for a best practice book and so on, by level of complexity and relevance. I have scoured the internet (or feels like it) to find such a list regarding FPGA, but at no luck so far, so thinking of posting the question here.

I have looked at three books for continued learning after I'm finished with Pong

Volnei Pedroni: Circuit Design and Simulation with VHDL ; seems to be aimed at explaining deeper the differences beetwen syntezisable and simulated VHDL. Though it seem to go through the VHDL language constructs yet again perhaps it is too much overlapping with Pong and Ashenden

Volnei Pedroni: Finite State Machines in Hardware: Theory and Design ; seems a good continuation, I understand that FSM is a very important topic in HW world and that they are completely different from SW FSM, also it seem to have excersises after each chapter which is good.

Pong Chu - RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability ; seems good, no more comments.

Thats my thinking, any suggestions or comments? Have not come about any books regarding FPGA testing? Perhaps I should look outside the more hands on book to one of the "meta" books out there?

May I recommend an IP stack implemented in FPGA. It was simulated using the free VHDL simulator: GHDL. It was synthesized using xilinx free tool and simulated again with post NGD net-list. All scripts and explanations are at:
http://bknpk.ddns.net/my_web/IP_STACK/start_1.html