Lattice Diamond/LSE Synthesis - implementing ring oscilator in Verilog ?...

[Brane 2]

I can\'t do it.

Every time I try, LSE reports \"combinatorial loop\" and optimizes whole thing away. I tried using attributes syn_preserve, syn_keep and syn_noprune, but the result is the same.

LSE Manual doesn\'t seem to list any more tricks that I could use or so it seems.

IS there any specific trick for this ?

I want to implement it to get a feeling about performance of some internal delays and it also seems useful for othrer things (RNG, temperature measurement etc).

If it means anything, I\'m doing it on Diamond 3.11 and MachXO2 Brakout board...

 

[Rick C]

On Sunday, June 14, 2020 at 2:18:11 AM UTC-4, Brane 2 wrote:

I can\'t do it.

Every time I try, LSE reports \"combinatorial loop\" and optimizes whole thing away. I tried using attributes syn_preserve, syn_keep and syn_noprune, but the result is the same.

LSE Manual doesn\'t seem to list any more tricks that I could use or so it seems.

IS there any specific trick for this ?

I want to implement it to get a feeling about performance of some internal delays and it also seems useful for othrer things (RNG, temperature measurement etc).

If it means anything, I\'m doing it on Diamond 3.11 and MachXO2 Brakout board...

Are you running an output to a pin? Try using a gate with an input from a pin that is held high or low, like an enable. I don\'t think it actually understand this is an oscillator. Rather it just optimizes things that don\'t \"matter\" in logical terms like having no input or no output. In the former case it sees the output as never changing and in the latter case it figures anything that can\'t impact an output can\'t be worth saving. It optimizes the logic away and so there\'s nothing to drive the nets, so the various \"keeps\" don\'t work since they are net attributes.

--

Rick C.

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[Brane 2]

I just tried it with I/O pin.

It seems to be working, but it\'s be nice to be able to do it without it.

There should be something akin to an attribute or pragma to switch loop detection off for that part.

Altera, Xilinx etc have examples for this. Can\'t find anything for Lattice.

 

[Rick C]

On Sunday, June 14, 2020 at 3:29:36 AM UTC-4, Brane 2 wrote:

I just tried it with I/O pin.

It seems to be working, but it\'s be nice to be able to do it without it.

There should be something akin to an attribute or pragma to switch loop detection off for that part.

Altera, Xilinx etc have examples for this. Can\'t find anything for Lattice.

I don\'t think it cares about the loop. Like I said, it should have an output so it isn\'t pointless. If your io pin on the input or output?

I think the optimization is for logic that has no output. I think their may be a switch to turn that off, but you likely don\'t want to use that for a real design because I\'ve seen synthesis generate macros that include extra logic that should be trimmed for outputs that aren\'t used. Not on do they generate it, the tool can give warnings about trimming superfluous logic and I like to get rid of all warnings. I also want that logic trimmed. That means manually checking all warnings to make sure they are acceptable. What a PITA.

--

Rick C.

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+ Tesla referral code - https://ts.la/richard11209

 

[Brane 2]

When my ring is connected to a counter ( and its MSB to an output pin), whole ring is simplpy ignored - counter input is left hanging.

LSE prints in the report that it detected combinatorial loop and that somehow all inverters are unused, so it drops them.

Same if I implement ring with XORs. But once I connected input of one of them to an extra input pin ( with a pull-up), things started working.

 

[Kevin Neilson]

On Sunday, June 14, 2020 at 12:18:11 AM UTC-6, Brane 2 wrote:

I can\'t do it.

Every time I try, LSE reports \"combinatorial loop\" and optimizes whole thing away. I tried using attributes syn_preserve, syn_keep and syn_noprune, but the result is the same.

LSE Manual doesn\'t seem to list any more tricks that I could use or so it seems.

IS there any specific trick for this ?

I want to implement it to get a feeling about performance of some internal delays and it also seems useful for othrer things (RNG, temperature measurement etc).

If it means anything, I\'m doing it on Diamond 3.11 and MachXO2 Brakout board...

Brane: I looked up some code I wrote a few years ago to create a ring oscillator which I used in the lab for error generation. This was for a Xilinx, so this might not be helpful, but in the comments I wrote that if I didn\'t instantiate the primitive, the logic would be pruned. Apparently I had originally written RTL and that didn\'t work. I had to instantiate the LUT primitive and initialize the lookup with 8\'h96 to make it a 3-input XOR (which is what I needed for this application). I also had to use the Xilinx (*DONT_TOUCH=\"true\"*) meta-comment.

I could paste in some code but it probably wouldn\'t help since it\'s Xilinx.

By the way, if you want to make a TRNG, search for this paper:
\"High Speed True Random Number Generators in Xilinx FPGAs,\" Catalin Baetoniu, Xilinx.

 

[Brane 2]

Thanks fore the tip.

WRT to oscillator - I\'ve redone it with LUT tables instead of inverters and now it works - LSE doesn\'t seem to be able to optimize it away.