Issue with file operations in verilog...

[GAYATHRI U]

module(input clk);
integer fd;
initial begin
fd = $fopen(\"log.txt\",\"w\");
for(int i =0;i<5;i =i+1)
begin
$fdisplay(fd,\"VALUE OF i %d \",i);
end

end
always @(posedge clk)
begin
$fdisplay(fd,\"TRANSACTION COMPLETE\");
end
endmodule

I am a user of Verilog.Can you please guide me in clearing this doubt.

The display \"Value of i \" will be stored in the text file log.txt.

I would like to dump the display written inside the always begin end block in the same text file.
but the file handle fd will not be available in the always block right.


can you please suggest me so that i can dump all the displays in the code in the same text file.

 

[Gabor]

On Friday, 5/27/2022 7:56 AM, GAYATHRI U wrote:

module(input clk);
integer fd;
initial begin
fd = $fopen(\"log.txt\",\"w\");
for(int i =0;i<5;i =i+1)
begin
$fdisplay(fd,\"VALUE OF i %d \",i);
end

end
always @(posedge clk)
begin
$fdisplay(fd,\"TRANSACTION COMPLETE\");
end
endmodule

I am a user of Verilog.Can you please guide me in clearing this doubt.

The display \"Value of i \" will be stored in the text file log.txt.

I would like to dump the display written inside the always begin end block in the same text file.
but the file handle fd will not be available in the always block right.


can you please suggest me so that i can dump all the displays in the code in the same text file.

Did you actually try this code? It looks like it should work. The only
possible problems would be collisions if more than one process tries to
write to the file. For example if the positive edge of clk coincides
with time 0, you would have a race between the initial block and the
clocked process.

The other thing is that I don\'t see anything that closes the file, which
would help if you want to look at the file contents before you close the
simulation.

--
Gabor