IN and OUT of the same entity?

[glen herrmannsfeldt]

I have a design that gets errors from Xilinx ISE, which looks
fine to me. It connects IN and OUT ports together:

signal y105: std_logic;

a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK,
y105, open, OUTON, vcc, OUTON, vcc, y108e);


The first y105 is an IN to N109, the second is OUT.

ISE says: "Line 531: Formal <j1> has no actual or default value."

and <j1> is the port of the first y105.

There is a similar error when another instantiation also uses
IN and OUT ports, but not exactly the same way.

It seems to me a strange restriction. Is it supposed to do that?

-- glen

 

[glen herrmannsfeldt]

glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:

I have a design that gets errors from Xilinx ISE, which looks
fine to me. It connects IN and OUT ports together:

a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK,
y105, open, OUTON, vcc, OUTON, vcc, y108e);

The first y105 is an IN to N109, the second is OUT.

ISE says: "Line 531: Formal <j1> has no actual or default value."

OK, maybe this was obvious to everyone else, but the file is
pretty big and I didn't notice. I forgot to say "port map".

I have no idea what it thinks it does, but it complains about
the third signal, j1. No obvious message like "you idiot, you forgot
to say PORT MAP:.

thanks, all.

-- glen

 

[rickman]

On 7/11/2015 7:58 PM, glen herrmannsfeldt wrote:

I have a design that gets errors from Xilinx ISE, which looks
fine to me. It connects IN and OUT ports together:

signal y105: std_logic;

a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK,
y105, open, OUTON, vcc, OUTON, vcc, y108e);


The first y105 is an IN to N109, the second is OUT.

ISE says: "Line 531: Formal <j1> has no actual or default value."

and <j1> is the port of the first y105.

There is a similar error when another instantiation also uses
IN and OUT ports, but not exactly the same way.

It seems to me a strange restriction. Is it supposed to do that?

I think that depends on what you have inside the entity. Do you have
the same connection inside? lol just kidding

I'm not clear on what you are coding. Is this an entity declaration? I
see the entity keyword, but this is not the syntax for an entity
declaration. Is this something I missed in VHDL 2008?

--

Rick

 

[rickman]

On 7/11/2015 11:30 PM, glen herrmannsfeldt wrote:

glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:
I have a design that gets errors from Xilinx ISE, which looks
fine to me. It connects IN and OUT ports together:

a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK,
y105, open, OUTON, vcc, OUTON, vcc, y108e);

The first y105 is an IN to N109, the second is OUT.

ISE says: "Line 531: Formal <j1> has no actual or default value."

OK, maybe this was obvious to everyone else, but the file is
pretty big and I didn't notice. I forgot to say "port map".

I have no idea what it thinks it does, but it complains about
the third signal, j1. No obvious message like "you idiot, you forgot
to say PORT MAP:.

thanks, all.

Lol, I thought it was messed up but I didn't want to assume I was right
and you were wrong. It has been well over a year since I've written any
VHDL and maybe a lot longer than that. Glad you figured it out.
Compilers can be pretty retarded about reporting what is really wrong.

I'm still not clear on the entity part. The keyword "entity" needs to
be removed too, right?

You are using positional association in your association list. I always
use named association. It is more to type, but prevents some types of
hard to find mistakes and might help the tools report better error
messages. It is not hard to use an editor macro to create the named
association list for a component instantiation and some tools will
create it for you. I make it from the port declaration of the entity.
That is one of the "issues" of VHDL... the excessive typing.... or do I
want to say incessant as in, "I can't take the incessant beating of the
jungle drums!" or in this case, "I can't take the incessant typing of
the Smith Corona!"

--

Rick

 

[glen herrmannsfeldt]

rickman <gnuarm@gmail.com> wrote:

(snip, I wrote)

a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK,
y105, open, OUTON, vcc, OUTON, vcc, y108e);

(snip, then I wrote)

OK, maybe this was obvious to everyone else, but the file is
pretty big and I didn't notice. I forgot to say "port map".

(snip)

Lol, I thought it was messed up but I didn't want to assume I was right
and you were wrong. It has been well over a year since I've written any
VHDL and maybe a lot longer than that. Glad you figured it out.
Compilers can be pretty retarded about reporting what is really wrong.

I am more used to verilog, but if I put the VHDL words in the
right place, it mostly works.

I mostly write structural verilog, and so now structural VHDL.

I'm still not clear on the entity part. The keyword "entity"
needs to be removed too, right?

No, the word entity is right.

I didn't completely figure it out, but there is component and
entity, where entity has the keyword.

You are using positional association in your association list. I always
use named association. It is more to type, but prevents some types of
hard to find mistakes and might help the tools report better error
messages. It is not hard to use an editor macro to create the named
association list for a component instantiation and some tools will
create it for you. I make it from the port declaration of the entity.
That is one of the "issues" of VHDL... the excessive typing.... or do I
want to say incessant as in, "I can't take the incessant beating of the
jungle drums!" or in this case, "I can't take the incessant typing of
the Smith Corona!"

The design is based on a TTL design, so the entities are TTL ICs.

I thought about the other way, but in either case I need to go
carefully through the design and verify the ports. There are a
lot of 74109 and 74161, so once I figure out the order for each,
I just have to verify them. The signal names are the original
names, which often don't mean much to me. Sometiems I have to
make a name, mostly for TTL gates. (I use entity for everything
except simple gates, and the VHDL equivalent of continuous
assignment for gates.)

In most cases, I put the output ports first, then the input ports.
The 74109 is a dual FF, so it is out then in for the first,
and out then in for the second.

-- glen

 

[glen herrmannsfeldt]

rickman <gnuarm@gmail.com> wrote:

(snip, I wrote)

I am more used to verilog, but if I put the VHDL words in the
right place, it mostly works.

I mostly write structural verilog, and so now structural VHDL.

So why are you using VHDL instead of Verilog? I've wanted to learn
Verilog for some time now, but when I am doing paid work I stick to what
I know. I haven't done a "for fun" HDL project in a while so I haven't
done much with Verilog.

It wasn't my choice.

I'm still not clear on the entity part. The keyword "entity"
needs to be removed too, right?

No, the word entity is right.

I didn't completely figure it out, but there is component and
entity, where entity has the keyword.

"Entity" is used to define the parameter list of an entity. It seems I
was unaware that it can also be used in a component instantiation when
you wish to skip having a component declaration. A component
declaration is like a function prototype in C, it defines the interface
for local use. By adding the keyword "entity" to the component
instantiation it eliminates the need for the component declaration.
However, this is now called an "entity" instantiation and will not work
with configurations... very complex...

I think that is the way I understand it.

Since verilog doesn't require the declaration, I didn't think that
VHDL should. Then I found out about entity and used that.

I still have comments explaining the order, the way I want to
read them.

You are using positional association in your association list. I always
use named association. It is more to type, but prevents some types of
hard to find mistakes and might help the tools report better error
messages.

(snip)

The design is based on a TTL design, so the entities are TTL ICs.

Should I assume this means the parameters are in pin number order?
Sounds like spice, but that doesn't make it good. You can still use
named association.

No, they aren't in that order on the original. I choose the
order that I like.

(snip)

In most cases, I put the output ports first, then the input ports.
The 74109 is a dual FF, so it is out then in for the first,
and out then in for the second.

If you use pin number based names for the TTL entities, you could use
named association which would make the verification trivial, well,
assuming you are copying this from a pin number oriented list of some
sort. Otherwise, why use TTL devices?

P01 => ralph,
P02 => betty,
...

You may be unpleasantly surprised at how easy it is to make a mistake
using positional association.

I have been doing Fortran and C programming for years, and I know
that it can be a problem. But we live with it in those cases.
(Fortran now allows for names, but most don't use them. But it
didn't when I first started.)

-- glen

 

[rickman]

On 7/12/2015 5:17 AM, glen herrmannsfeldt wrote:

rickman <gnuarm@gmail.com> wrote:

(snip, I wrote)

a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK,
y105, open, OUTON, vcc, OUTON, vcc, y108e);

(snip, then I wrote)
OK, maybe this was obvious to everyone else, but the file is
pretty big and I didn't notice. I forgot to say "port map".

(snip)

Lol, I thought it was messed up but I didn't want to assume I was right
and you were wrong. It has been well over a year since I've written any
VHDL and maybe a lot longer than that. Glad you figured it out.
Compilers can be pretty retarded about reporting what is really wrong.

I am more used to verilog, but if I put the VHDL words in the
right place, it mostly works.

I mostly write structural verilog, and so now structural VHDL.

So why are you using VHDL instead of Verilog? I've wanted to learn
Verilog for some time now, but when I am doing paid work I stick to what
I know. I haven't done a "for fun" HDL project in a while so I haven't
done much with Verilog.

I'm still not clear on the entity part. The keyword "entity"
needs to be removed too, right?

No, the word entity is right.

I didn't completely figure it out, but there is component and
entity, where entity has the keyword.

"Entity" is used to define the parameter list of an entity. It seems I
was unaware that it can also be used in a component instantiation when
you wish to skip having a component declaration. A component
declaration is like a function prototype in C, it defines the interface
for local use. By adding the keyword "entity" to the component
instantiation it eliminates the need for the component declaration.
However, this is now called an "entity" instantiation and will not work
with configurations... very complex...

You are using positional association in your association list. I always
use named association. It is more to type, but prevents some types of
hard to find mistakes and might help the tools report better error
messages. It is not hard to use an editor macro to create the named
association list for a component instantiation and some tools will
create it for you. I make it from the port declaration of the entity.
That is one of the "issues" of VHDL... the excessive typing.... or do I
want to say incessant as in, "I can't take the incessant beating of the
jungle drums!" or in this case, "I can't take the incessant typing of
the Smith Corona!"

The design is based on a TTL design, so the entities are TTL ICs.

Should I assume this means the parameters are in pin number order?
Sounds like spice, but that doesn't make it good. You can still use
named association.

I thought about the other way, but in either case I need to go
carefully through the design and verify the ports. There are a
lot of 74109 and 74161, so once I figure out the order for each,
I just have to verify them. The signal names are the original
names, which often don't mean much to me. Sometiems I have to
make a name, mostly for TTL gates. (I use entity for everything
except simple gates, and the VHDL equivalent of continuous
assignment for gates.)

In most cases, I put the output ports first, then the input ports.
The 74109 is a dual FF, so it is out then in for the first,
and out then in for the second.

If you use pin number based names for the TTL entities, you could use
named association which would make the verification trivial, well,
assuming you are copying this from a pin number oriented list of some
sort. Otherwise, why use TTL devices?

P01 => ralph,
P02 => betty,
....

You may be unpleasantly surprised at how easy it is to make a mistake
using positional association.

--

Rick