IEEE Std 1076-2019

[HT-Lab]

For those of you who are not on the VHDL-200X mailing list it looks like
IEEE has finally ratified VHDL2019, it is now an official IEEE standard:
IEEE Std 1076-2019

Thanks to Jim Lewis and the volunteers for all the hard work and not
giving up under all the SV pressure ;-)

Hans
www.ht-lab.com

 

[Rick C]

On Friday, September 6, 2019 at 5:47:05 AM UTC-4, HT-Lab wrote:

For those of you who are not on the VHDL-200X mailing list it looks like
IEEE has finally ratified VHDL2019, it is now an official IEEE standard:
IEEE Std 1076-2019

Thanks to Jim Lewis and the volunteers for all the hard work and not
giving up under all the SV pressure ;-)

Hans
www.ht-lab.com

Interesting. I wonder what the impacts will be.

64 bit integer. Seems like this is the default, not an option to be specified. I expect this will have an impact on some code that works with the 32 bit default. Much like in other languages which don't specify the size of integer data types, rather just minimums, I expect coding will change in VHDL to make all use of integers work with ranges (other than 64 bit integers of course). So if you had assumed 32 bits, you will need to specify a sub-type with a 32 bit integer range. I suppose this won't break code but it can result in wasteful additional resources used.

Conditional compilation sounds useful.

I wonder which features will be supported in tools first? I wonder which features will be supported at all?

--

Rick C.

- Get 1,000 miles of free Supercharging
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[HT-Lab]

On 06/09/2019 18:00, Rick C wrote:

On Friday, September 6, 2019 at 5:47:05 AM UTC-4, HT-Lab wrote:
For those of you who are not on the VHDL-200X mailing list it looks like
IEEE has finally ratified VHDL2019, it is now an official IEEE standard:
IEEE Std 1076-2019

Thanks to Jim Lewis and the volunteers for all the hard work and not
giving up under all the SV pressure ;-)

Hans
www.ht-lab.com

Interesting. I wonder what the impacts will be.

I suspect very little to start with but I am hoping Jim Lewis will
create again one of his VHDL presentations which will point out all the
goodies.

64 bit integer. Seems like this is the default, not an option to be specified. I expect this will have an impact on some code that works with the 32 bit default.

I assume vendors will keep the same behaviour unless the user specifies
VHDL2019.

Much like in other languages which don't specify the size of integer
data types, rather just minimums, I expect coding will change in VHDL to
make all use of integers work with ranges (other than 64 bit integers of
course). So if you had assumed 32 bits, you will need to specify a
sub-type with a 32 bit integer range. I suppose this won't break code
but it can result in wasteful additional resources used.

Conditional compilation sounds useful.

I fully agree, I know a lot of engineers advocate that pragma's lead to
spaghetti code as seen in C/C++ and other languages but to have zero
support is no solution either. I use a home grown preprocessor on my
code for many years and it made my life a lot easier not to mention
reduced the number of synthesis warning.

I wonder which features will be supported in tools first? I wonder which features will be supported at all?

Aldec's Riviera apparently already supports some features, not sure
which one but the preprocessor is probably the simplest one as they can
lift it straight from SV.

Perhaps a Riviera user can confirm this?

Hans
www.ht-lab.com

I wonder which features will be supported at all?

>

 

[HT-Lab]

On 06/09/2019 10:47, HT-Lab wrote:

For those of you who are not on the VHDL-200X mailing list it looks like
IEEE has finally ratified VHDL2019, it is now an official IEEE standard:
IEEE Std 1076-2019

Thanks to Jim Lewis and the volunteers for all the hard work and not
giving up under all the SV pressure ;-)

Hans
www.ht-lab.com

It has just been pointed out to me that although VHDL2019 is ratified by
the IEEE it has not yet been released, this might take some time but
hopefully should happen before the end of the year. Note that VHDL2008
was released in 2009.

I guess this is the reason why we don't see any press releases, we need
to wait until the LRM is printed and be made available to the general
public.

Hans
www.ht-lab.com

 

[Rick C]

On Wednesday, September 25, 2019 at 12:06:29 PM UTC-4, HT-Lab wrote:

On 06/09/2019 10:47, HT-Lab wrote:
For those of you who are not on the VHDL-200X mailing list it looks like
IEEE has finally ratified VHDL2019, it is now an official IEEE standard:
IEEE Std 1076-2019

Thanks to Jim Lewis and the volunteers for all the hard work and not
giving up under all the SV pressure ;-)

Hans
www.ht-lab.com

It has just been pointed out to me that although VHDL2019 is ratified by
the IEEE it has not yet been released, this might take some time but
hopefully should happen before the end of the year. Note that VHDL2008
was released in 2009.

I guess this is the reason why we don't see any press releases, we need
to wait until the LRM is printed and be made available to the general
public.

Hans
www.ht-lab.com

"Printed"??? Really, they want to "print" the document? Does that take more than 15 minutes? I guess 5 minutes to generate the PDF file and 10 minutes to send it to the printer?

--

Rick C.

- Get 2,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[HT-Lab]

On 25/09/2019 17:15, Rick C wrote:

On Wednesday, September 25, 2019 at 12:06:29 PM UTC-4, HT-Lab wrote:
On 06/09/2019 10:47, HT-Lab wrote:
For those of you who are not on the VHDL-200X mailing list it looks like
IEEE has finally ratified VHDL2019, it is now an official IEEE standard:
IEEE Std 1076-2019

Thanks to Jim Lewis and the volunteers for all the hard work and not
giving up under all the SV pressure ;-)

Hans
www.ht-lab.com

It has just been pointed out to me that although VHDL2019 is ratified by
the IEEE it has not yet been released, this might take some time but
hopefully should happen before the end of the year. Note that VHDL2008
was released in 2009.

I guess this is the reason why we don't see any press releases, we need
to wait until the LRM is printed and be made available to the general
public.

Hans
www.ht-lab.com

"Printed"??? Really, they want to "print" the document? Does that take more than 15 minutes? I guess 5 minutes to generate the PDF file and 10 minutes to send it to the printer?

Of course printed means a whole range of admin/marketing/bureaucratic
tasks, I suspect that even getting the webpage sorted out will take a
few weeks.

Now an interesting questions is if the IEEE will make the standard
freely available like they do for SV/SystemC or paid for like they do
for VHDL2008/PSL.....never mind.

Hans
www.ht-lab.com

 

[Rick C]

On Wednesday, September 25, 2019 at 1:07:14 PM UTC-4, HT-Lab wrote:

On 25/09/2019 17:15, Rick C wrote:
On Wednesday, September 25, 2019 at 12:06:29 PM UTC-4, HT-Lab wrote:
On 06/09/2019 10:47, HT-Lab wrote:
For those of you who are not on the VHDL-200X mailing list it looks like
IEEE has finally ratified VHDL2019, it is now an official IEEE standard:
IEEE Std 1076-2019

Thanks to Jim Lewis and the volunteers for all the hard work and not
giving up under all the SV pressure ;-)

Hans
www.ht-lab.com

It has just been pointed out to me that although VHDL2019 is ratified by
the IEEE it has not yet been released, this might take some time but
hopefully should happen before the end of the year. Note that VHDL2008
was released in 2009.

I guess this is the reason why we don't see any press releases, we need
to wait until the LRM is printed and be made available to the general
public.

Hans
www.ht-lab.com

"Printed"??? Really, they want to "print" the document? Does that take more than 15 minutes? I guess 5 minutes to generate the PDF file and 10 minutes to send it to the printer?

Of course printed means a whole range of admin/marketing/bureaucratic
tasks, I suspect that even getting the webpage sorted out will take a
few weeks.

It would seem to be an inefficient organization that does all that completely serially.

Now an interesting questions is if the IEEE will make the standard
freely available like they do for SV/SystemC or paid for like they do
for VHDL2008/PSL.....never mind.

A trick they use with some standards is to take advantage of the fact that they can release all but the final version. Make some totally insignificant change in the final release and the standard version document before that change can still be freely circulated. A standard that no one reads is not of much value.

--

Rick C.

-- Get 2,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209