how to use "adc_dnl_8bit" for DNL simulation?

I'm wondering if there are detailed documentation for the usage of
adc_dnl_8bit... Thanks!

 

Dear Andrew (and others),

Thank you so much for your quick reply!! Since I'm fairly new to this,
I still have a few things which are not clear.

1. You mentioned "this block generates the clock pulse and voltage
input for
the ADC under test". But I remembered in the adc_dnl_8bit block, vout
is the only output, and vclk is supposed to be an input terminal, how
could we feed these two into the ADC under test?

2. What I was doing is, I use a ramp source as the input for the
ADC_under_test, whose outputs go into adc_dnl_8bit block, and I use a
clock source to feed into the both blocks (ADC_under_test and
adc_dnl_8bit block), but I keep getting error: the net29 (i.e., vclk of
adc_dnl_8bit block) forms a rigid loop (shorts) when added to circuit
(Vclk: 0). Could you advise what's wrong here?

3. What exactly is the output of adc_dnl_8bit block? How can we get the
DNL plot directly out of it?

Many thanks! Your help will save me days of time, so I really
appreciate your previous time!

 

Andrew Beckett wrote:

Ah, I see the problem. The pin on the symbol is an input pin. Well, it
shouldn't be, and that's a bug. I'll file a PCR for that.

I filed PCR 802181 to get this pin direction corrected.

What is adc_dnl_8bit?
Is it IP that Cadence do provide?
Or is it IEEE IP?
Or what?

 

Thank you, Andrew!

After played around it for a while, I think I'm getting close there.
Here is another question.

Regardless how I change the values in the CDF form of the blocks, the
values actually never change. I have to go into the source file to edit
them. Could this be a bug?

Also, where's the default location for the log file? Is input.dat under
netlist/ the correct result file?

Many thanks!!!

 

Thank you, Andrew! Is input.dat the output file which contains the
DNL's for all the codes?

 

On Wednesday, May 25, 2005 11:48:11 AM UTC+5:30, wjc...@yahoo.com wrote:

I'm wondering if there are detailed documentation for the usage of
adc_dnl_8bit... Thanks!

Hi,,

I am running DNL veriloga code but input.dat file is not created in the directory.Can anyone help me on this? Why its not getting created.do I need to change something in code?

Thanks

 

[Andrew Beckett]

On 03/26/13 10:10, check123out@gmail.com wrote:

On Wednesday, May 25, 2005 11:48:11 AM UTC+5:30, wjc...@yahoo.com wrote:
I'm wondering if there are detailed documentation for the usage of
adc_dnl_8bit... Thanks!

Hi,,

I am running DNL veriloga code but input.dat file is not created in
the directory.Can anyone help me on this? Why its not getting created.do

I need to change something in code?

Thanks

Did you set log_to_file to be 1? (i.e. non-zero). Also, the file (if you
specify a path which is not a full path) will get written into the
netlist directory if running from ADE.

Maybe you can post the bit of your netlist (input.scs if using ADE)
which instantiates the adc_dnl_8bit ?

Regards,

Andrew.

 

[Ping]

On Wednesday, May 25, 2005 at 2:18:11 AM UTC-4, wjc...@yahoo.com wrote:

I'm wondering if there are detailed documentation for the usage of
adc_dnl_8bit... Thanks!

Hi, I am trying to figure out how to use this "adc_dnl_8bit" too (simulate by ADE L). I have some questions... (the adc_dnl_8bit version, according to the cdoe, is 1.1, Data: 1997/08/28)

vstart = voltage at which to start conversion sweep
vend = voltage at which to end conversion sweep
What're these two parameter for? The test is using histogram method. So does this mean it's using ramp or sin signal as input?

I am using an ideal 8bit ADC (verilog-A code) to test the simulation result. But I don't know which analyses should use. So I tried .tran. The result of input.dat is -1 for all codes. Which analyses should I set and how to set it?

And how to specify a full path for this output file? And when I set the filename, it seems the output file is still input.dat.

 

Hii Andrew,
I followed your instruction for calculating the dnl of the adc, but I am not getting the dnl values. The values of width and dnl all are coming zeros. Why it comes I am not understand please instruct me.