how to use 74hc74

I

iceman

Guest
anyone have a schematic how to use 74hc74... i cant make it work...tnx
 
"iceman" <static123ph@yahoo.com> wrote
anyone have a schematic how to use 74hc74... i cant make it work...tnx
Why don't you just show us your schematic? Do you have the /S and /R
pins tied high? If they are both low, the Q outputs will both be high.
If either is a logic low, then the Q outputs will reflect that.
Otherwise if the /S and /R pins are both high, the D input will clock to
the Q and /Q outputs on the rising edge of a clock signal. What are you
trying to do that is not working?
 
"iceman" <static123ph@yahoo.com> wrote in message
news:62011d8f.0501271729.4302f7a6@posting.google.com...
anyone have a schematic how to use 74hc74... i cant make it work...tnx
Make sure you have a bypass capacitor between VCC and GND, and don't leave
any input pins unconnected.

Tam
 
One must have some kind of pinout to attempt to try, to be able to say it
doesnt work. Id suggest that since its an HC device, it may already have
been zapped by static/ESD and should now be used for artwork.

Try to find the 74S74, or the AS type, the HC is hypersensitive to static


"Tam/WB2TT" <t-tammaru@c0mca$t.net> wrote in message
news:pv-dnXbdB_U4VGTcRVn-hg@comcast.com...
"iceman" <static123ph@yahoo.com> wrote in message
news:62011d8f.0501271729.4302f7a6@posting.google.com...
anyone have a schematic how to use 74hc74... i cant make it work...tnx

Make sure you have a bypass capacitor between VCC and GND, and don't leave
any input pins unconnected.

Tam
 
On Fri, 28 Jan 2005 01:29:46 UTC, static123ph@yahoo.com (iceman)
wrote:

anyone have a schematic how to use 74hc74... i cant make it work...tnx
The 7474 is (IIRC) a single D flip flop. Do you understand the
different sorts of flip flop? A D flip flop latches the information on
the D input to the Q output on an active transition of the clock
input. If you wanted to make it divide by 2 you connect the ~Q (Q_bar)
output to the D input. the output will change state for each transtion
of the clock in the active direction (ie rising or falling).

As other posters have pointed out, make sure you have a clean clock
signal, that the chip is decoupled and that the set and reset input
are tied to the correct logic level.

--
Jim Backus OS/2 user since 1994
bona fide replies to j <dot> backus <the circle thingy> jita <dot>
demon <dot> co <dot> uk
 

Welcome to EDABoard.com

Sponsor

Back
Top