V
Very Very Log
Guest
Hello,
I am new to designing registers and buses in Verilog.
Can someone let me know how can I learn the same?
Any good books or tutorials on the net?
I am basically looking for clear explanations on chip-select, read-not-
write, word_size, periph_ctl, periph_stat, fful, fempty, end-of-
packet, acknowledge etc.
Also, I want details of designing with registers in (System)Verilog
Thanks
Techieeee
I am new to designing registers and buses in Verilog.
Can someone let me know how can I learn the same?
Any good books or tutorials on the net?
I am basically looking for clear explanations on chip-select, read-not-
write, word_size, periph_ctl, periph_stat, fful, fempty, end-of-
packet, acknowledge etc.
Also, I want details of designing with registers in (System)Verilog
Thanks
Techieeee