How to instantiate a verilog block inside a VHDL entity?

[thunder]

Hello


My design consists of VHDL blocks. Now i need to instantiate a verilog block inside my VHDL block.

QS: Is it possible to instantiate a verilog block inside a VHDL block?
QS: If the answer to the above question is yes, how to achieve this?

Thanks in advance

JO

 

[Paul Uiterlinden]

thunder wrote:

Hello


My design consists of VHDL blocks. Now i need to instantiate a verilog
block inside my VHDL block.

QS: Is it possible to instantiate a verilog block inside a VHDL block?

Yes.

> QS: If the answer to the above question is yes, how to achieve this?

Declare a component for the Verilog module and instantiate it just like any
other VHDL component.

Check your simulator user's manual for details.

--
Paul Uiterlinden
AimValley

 

[Allan Herriman]

On Mon, 17 Feb 2014 01:03:27 -0800, thunder wrote:

Hello


My design consists of VHDL blocks. Now i need to instantiate a verilog
block inside my VHDL block.

QS: Is it possible to instantiate a verilog block inside a VHDL block?
QS: If the answer to the above question is yes, how to achieve this?

Thanks in advance

My experience is that it is possible to instantiate a verilog module
inside a VHDL architecture, both using component instantiation and entity
instantiation, in most tools, for both synthesis and simulation.

Significantly, Altera Quartus does not allow entity instantiation, which
means if you want Altera compatibility you will need to write a component
declaration for each Verilog module.

Things that don't work the way you'd want:
- heirarchical references typically can't go across a VHDL/Verilog
boundary.

Things to avoid for portability:
- (for ports) types other than std_logic, std_logic_vector
- (for generics/parameters) types other than integer and string
- in some tools (e.g. older Modelsim), port mappings can only be to
signals. It is not possible to map a port to a constant, for example.


Example:

module foo
#(
parameter bar = 1
)
(
input wire bletch,
output reg baz = 1'b0
);

You could instantiate this as an entity, provided that it has already
been compiled into the work library:

some_label : entity work.foo
generic map (
bar => 2
)
port map (
bletch => signal1,
baz => signal2
);

Or if you really like typing you could instantiate module foo as a
component:

component foo is
generic (
bar : integer := 1
);
port (
bletch : in std_logic;
baz : out std_logic
);
end component foo;

....

some_label : component foo
generic map (
bar => 2
)
port map (
bletch => signal1,
baz => signal2
);

Note that the keyword "component" is optional in a component
instantiation. Most people leave it out.

Regards,
Allan

 

[GaborSzakacs]

Allan Herriman wrote:

On Mon, 17 Feb 2014 01:03:27 -0800, thunder wrote:

Hello


My design consists of VHDL blocks. Now i need to instantiate a verilog
block inside my VHDL block.

QS: Is it possible to instantiate a verilog block inside a VHDL block?
QS: If the answer to the above question is yes, how to achieve this?

Thanks in advance

My experience is that it is possible to instantiate a verilog module
inside a VHDL architecture, both using component instantiation and entity
instantiation, in most tools, for both synthesis and simulation.

Significantly, Altera Quartus does not allow entity instantiation, which
means if you want Altera compatibility you will need to write a component
declaration for each Verilog module.

Things that don't work the way you'd want:
- heirarchical references typically can't go across a VHDL/Verilog
boundary.

Things to avoid for portability:
- (for ports) types other than std_logic, std_logic_vector
- (for generics/parameters) types other than integer and string
- in some tools (e.g. older Modelsim), port mappings can only be to
signals. It is not possible to map a port to a constant, for example.


Example:

module foo
#(
parameter bar = 1
)
(
input wire bletch,
output reg baz = 1'b0
);

You could instantiate this as an entity, provided that it has already
been compiled into the work library:

some_label : entity work.foo
generic map (
bar => 2
)
port map (
bletch => signal1,
baz => signal2
);

Or if you really like typing you could instantiate module foo as a
component:

component foo is
generic (
bar : integer := 1
);
port (
bletch : in std_logic;
baz : out std_logic
);
end component foo;

...

some_label : component foo
generic map (
bar => 2
)
port map (
bletch => signal1,
baz => signal2
);

Note that the keyword "component" is optional in a component
instantiation. Most people leave it out.

Regards,
Allan

The last time I did this with Xilinx tools (ISE) I found I needed to use
a component instantiation. However I didn't need to do much typing
because once you add the verilog module to the project you can "View
instantiation template" which generates the required component
declaration as well as the instantiation template to paste into your
VHDL code.

Some other things to avoid are Verilog port names with upper and lower
case, especially not having ports that differ *only* in the case of
the name like:

module foobar
(
input wire FOO,
input wire Foo,
output reg foo
);

which is legal Verilog, but can wreak havoc when you try to instantiate
it from VHDL.

--
Gabor

 

[Allan Herriman]

On Mon, 17 Feb 2014 16:26:35 -0500, GaborSzakacs wrote:

Allan Herriman wrote:
On Mon, 17 Feb 2014 01:03:27 -0800, thunder wrote:

Hello


My design consists of VHDL blocks. Now i need to instantiate a verilog
block inside my VHDL block.

QS: Is it possible to instantiate a verilog block inside a VHDL block?
QS: If the answer to the above question is yes, how to achieve this?

Thanks in advance

My experience is that it is possible to instantiate a verilog module
inside a VHDL architecture, both using component instantiation and
entity instantiation, in most tools, for both synthesis and simulation.

Significantly, Altera Quartus does not allow entity instantiation,
which means if you want Altera compatibility you will need to write a
component declaration for each Verilog module.

Things that don't work the way you'd want:
- heirarchical references typically can't go across a VHDL/Verilog
boundary.

Things to avoid for portability:
- (for ports) types other than std_logic, std_logic_vector - (for
generics/parameters) types other than integer and string - in some
tools (e.g. older Modelsim), port mappings can only be to signals. It
is not possible to map a port to a constant, for example.


Example:

module foo #(
parameter bar = 1
)
(
input wire bletch, output reg baz = 1'b0
);

You could instantiate this as an entity, provided that it has already
been compiled into the work library:

some_label : entity work.foo generic map (
bar => 2
)
port map (
bletch => signal1, baz => signal2
);

Or if you really like typing you could instantiate module foo as a
component:

component foo is generic (
bar : integer := 1
);
port (
bletch : in std_logic;
baz : out std_logic
);
end component foo;

...

some_label : component foo generic map (
bar => 2
)
port map (
bletch => signal1, baz => signal2
);

Note that the keyword "component" is optional in a component
instantiation. Most people leave it out.

Regards,
Allan

The last time I did this with Xilinx tools (ISE) I found I needed to use
a component instantiation.

Entity instantiation of Verilog in VHDL works as far back as ISE 6.3
(possibly earlier, but that is the oldest version I can test right now).
A co-worker advised that it's broken again in ISE 14.7 for Virtex 4 but
not Virtex 6 or 7 targets - something to do with the "old" parser and
"new" parser switch. I haven't tried it in Vivado yet.

Some other things to avoid are Verilog port names with upper and lower
case, especially not having ports that differ *only* in the case of the
name like:

module foobar (
input wire FOO,
input wire Foo,
output reg foo
);

which is legal Verilog, but can wreak havoc when you try to instantiate
it from VHDL.

Another thing that has bitten me in the past was port names that are VHDL
keywords. "In" and "out" seem popular port names in Verilog, and don't
work so well in VHDL.

I also recall that an old Xilinx Unisim model (CLBRAM, I think) had a
port called "do" (data output) which causes probnlems for the same reason.

Regards,
Allan

 

[GaborSzakacs]

Allan Herriman wrote:

On Mon, 17 Feb 2014 16:26:35 -0500, GaborSzakacs wrote:

Allan Herriman wrote:

[snip]

Another thing that has bitten me in the past was port names that are VHDL
keywords. "In" and "out" seem popular port names in Verilog, and don't
work so well in VHDL.

I also recall that an old Xilinx Unisim model (CLBRAM, I think) had a
port called "do" (data output) which causes probnlems for the same reason.

Regards,
Allan

I've seen other weird problems in XST with mixed language projects. For
example I found that if I had code in Verilog and VHDL that each used
the same library primitive (e.g. RAMB16_S9_S9) XST would rename one of
them with a suffix (e.g. RAMB16_S9_S9_1) and then barf because it
couldn't find the renamed unit in any library. In general I've found
mixed language projects to be a headache.

--
Gabor

 

[Daniel Kho]

Significantly, Altera Quartus does not allow entity instantiation, which

means if you want Altera compatibility you will need to write a component

declaration for each Verilog module.

I suggest for those who like to see this feature supported by Quartus, file a mySupport case with Altera (if you have enough privileges), or submit a post in Altera Forums.

Based on my experience with Altera, they have the habit of prioritising work based on number of requests filed on a particular topic. If there are many requests regarding a single issue, that issue will receive more attention.

-daniel

 

[LeRoss Calnek]

very helpful

thanks

On Monday, 17 February 2014 06:46:24 UTC-6, Allan Herriman wrote:

On Mon, 17 Feb 2014 01:03:27 -0800, thunder wrote:

Hello


My design consists of VHDL blocks. Now i need to instantiate a verilog
block inside my VHDL block.

QS: Is it possible to instantiate a verilog block inside a VHDL block?
QS: If the answer to the above question is yes, how to achieve this?

Thanks in advance

My experience is that it is possible to instantiate a verilog module
inside a VHDL architecture, both using component instantiation and entity
instantiation, in most tools, for both synthesis and simulation.

Significantly, Altera Quartus does not allow entity instantiation, which
means if you want Altera compatibility you will need to write a component
declaration for each Verilog module.

Things that don't work the way you'd want:
- heirarchical references typically can't go across a VHDL/Verilog
boundary.

Things to avoid for portability:
- (for ports) types other than std_logic, std_logic_vector
- (for generics/parameters) types other than integer and string
- in some tools (e.g. older Modelsim), port mappings can only be to
signals. It is not possible to map a port to a constant, for example.


Example:

module foo
#(
parameter bar = 1
)
(
input wire bletch,
output reg baz = 1'b0
);

You could instantiate this as an entity, provided that it has already
been compiled into the work library:

some_label : entity work.foo
generic map (
bar => 2
)
port map (
bletch => signal1,
baz => signal2
);

Or if you really like typing you could instantiate module foo as a
component:

component foo is
generic (
bar : integer := 1
);
port (
bletch : in std_logic;
baz : out std_logic
);
end component foo;

...

some_label : component foo
generic map (
bar => 2
)
port map (
bletch => signal1,
baz => signal2
);

Note that the keyword "component" is optional in a component
instantiation. Most people leave it out.

Regards,
Allan

 

[ABFAROUK]

Instantiating a Verilog Module in a VHDL Design Unit
In a mixed language design, you can instantiate a Verilog module in a VHDL design unit.
To Instantiate a Verilog Module in a VHDL Design Unit
Declare a VHDL component with the same name as the Verilog module (respecting case sensitivity) that you want to instantiate.
For example,
COMPONENT FD PORT (
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC );
END COMPONENT;
Use named association to instantiate the Verilog module.
For example,
UUT : FD PORT MAP(
Q => O,
D => I,
C => CLK);
Since Verilog is case sensitive, named associations and the local port names that you use in the component declaration must match the case of the corresponding Verilog port names.


On Monday, February 17, 2014 at 12:03:27 PM UTC+3, thunder wrote:

Hello


My design consists of VHDL blocks. Now i need to instantiate a verilog block inside my VHDL block.

QS: Is it possible to instantiate a verilog block inside a VHDL block?
QS: If the answer to the above question is yes, how to achieve this?

Thanks in advance

JO

 

[ABFAROUK]

and on the conterary:
Instantiating a VHDL Module in a Verilog Design Unit
In a mixed language design, you can instantiate a VHDL module in a Vesign design unit.
To Instantiate a VHDL Module in a Verilog Design Unit
Instantiate the VHDL entity as if it were a Verilog module.
For example,
module testbench ;
wire in, clk;
wire out;
FD FD1(
..Q(Q_OUT),
..C(CLK);
..D(A);
);


On Monday, February 17, 2014 at 12:03:27 PM UTC+3, thunder wrote:

Hello


My design consists of VHDL blocks. Now i need to instantiate a verilog block inside my VHDL block.

QS: Is it possible to instantiate a verilog block inside a VHDL block?
QS: If the answer to the above question is yes, how to achieve this?

Thanks in advance

JO