Help with VHDL architecture

[Olalekan Shittu]

Hello everyone.

I have been trying to write a VHDL architecture for the circuit below but doesn't seem to be making headway, can anyone be of help.

Below is my entity declaration from the system

Library ieee;
use IEEE.std_logic_1164.all;

entity Sorter IS
Port ( C: IN std_logic_vector (0 to 3);
Sel: IN STD_LOGIC_VECTOR(0 to 2);
out0: out std_logic;
out1: out std_logic;
out2: out std_logic;
out3: out std_logic
);
end sorter;

I am to write an architecture for the above with condition that:

When Sel equal 4, the resulting output as shown in the table below is generated

out0 out1 out2 out3
0 <= C < 4 1 0 0 0

4 <= C < 8 0 1 0 0

8 <= C < 12 0 0 1 0

12 <= C < 16 0 0 0 1

otherwise out0,out1,out2,out3 are all equal to zero.

Thanks

 

[Andy Bennett]

"Olalekan Shittu" wrote in message
news:622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com...

Hello everyone.

I have been trying to write a VHDL architecture for the circuit below but
doesn't seem to be making headway, can anyone be of help.

Below is my entity declaration from the system

Library ieee;
use IEEE.std_logic_1164.all;

entity Sorter IS
Port ( C: IN std_logic_vector (0 to 3);
Sel: IN STD_LOGIC_VECTOR(0 to 2);
out0: out std_logic;
out1: out std_logic;
out2: out std_logic;
out3: out std_logic
);
end sorter;

I am to write an architecture for the above with condition that:

When Sel equal 4, the resulting output as shown in the table below is
generated

out0 out1 out2 out3
0 <= C < 4 1 0 0 0

4 <= C < 8 0 1 0 0

8 <= C < 12 0 0 1 0

12 <= C < 16 0 0 0 1

otherwise out0,out1,out2,out3 are all equal to zero.

Thanks






Something like:-

Defaults:-

Out[3..0] = 0

End defaults

If C >= 0 or C < 4 then
out0 = 1
end if

If C >= 4 or C < 8 then
out1 = 1
end if

If C >= 8 or C < 12end if
out2 = 1
end if

If C >= 12 or C < 16 then
out3 = 1
end if

 

[Andy Bennett]

"Andy Bennett" wrote in message
news:O_2dnY2_V4Fi_DvJnZ2dnUVZ8nWdnZ2d@brightview.co.uk...

Forgot to add sel ... so







Something like:-

Defaults:-

Out[3..0] = 0

End defaults


If sel = 4 then
If C >= 0 or C < 4 then
out0 = 1
end if

If C >= 4 or C < 8 then
out1 = 1
end if

If C >= 8 or C < 12end if
out2 = 1
end if

If C >= 12 or C < 16 then
out3 = 1
end if
end if


The student can add/correct the syntax


Andy

 

[Olalekan Shittu]

On Friday, 2 January 2015 10:19:42 UTC+1, Andy Bennett wrote:

"Andy Bennett" wrote in message
news:O_2dnY2_V4Fi_DvJnZ2dnUVZ8nWdnZ2d@brightview.co.uk...

Forgot to add sel ... so







Something like:-

Defaults:-

Out[3..0] = 0

End defaults


If sel = 4 then
If C >= 0 or C < 4 then
out0 = 1
end if

If C >= 4 or C < 8 then
out1 = 1
end if

If C >= 8 or C < 12end if
out2 = 1
end if

If C >= 12 or C < 16 then
out3 = 1
end if
end if


The student can add/correct the syntax


Andy

Thanks Andy, trying to work on the syntax for now.

Is there a way I can combine this system with another system before writing a test bench for it. If you dont mind, I can send you a personal email.

 

On Saturday, 3 January 2015 11:38:20 UTC+1, Olalekan Shittu wrote:

On Friday, 2 January 2015 10:19:42 UTC+1, Andy Bennett wrote:
"Andy Bennett" wrote in message
news:O_2dnY2_V4Fi_DvJnZ2dnUVZ8nWdnZ2d@brightview.co.uk...

Forgot to add sel ... so







Something like:-

Defaults:-

Out[3..0] = 0

End defaults


If sel = 4 then
If C >= 0 or C < 4 then
out0 = 1
end if

If C >= 4 or C < 8 then
out1 = 1
end if

If C >= 8 or C < 12end if
out2 = 1
end if

If C >= 12 or C < 16 then
out3 = 1
end if
end if


The student can add/correct the syntax


Andy

Thanks Andy, trying to work on the syntax for now.

Is there a way I can combine this system with another system before writing a test bench for it. If you dont mind, I can send you a personal email.

What do you want to combine this with? It is a very simple if statement logic and can be combined easily i think.

 

On Friday, January 2, 2015 at 3:55:55 AM UTC-5, Olalekan Shittu wrote:

Hello everyone.

I have been trying to write a VHDL architecture for the circuit below but doesn't seem to be making headway, can anyone be of help.

Below is my entity declaration from the system

Library ieee;
use IEEE.std_logic_1164.all;

entity Sorter IS
Port ( C: IN std_logic_vector (0 to 3);
Sel: IN STD_LOGIC_VECTOR(0 to 2);
out0: out std_logic;
out1: out std_logic;
out2: out std_logic;
out3: out std_logic
);
end sorter;

I am to write an architecture for the above with condition that:

When Sel equal 4, the resulting output as shown in the table below is generated

out0 out1 out2 out3
0 <= C < 4 1 0 0 0

4 <= C < 8 0 1 0 0

8 <= C < 12 0 0 1 0

12 <= C < 16 0 0 0 1

otherwise out0,out1,out2,out3 are all equal to zero.

Thanks

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