Help!Why I get all zero for area, timing and power in Synops

[Li Yijun]

Hello,

I use Synopsys Design Analyzer to read a verilog file. It is complied
successfully. But why the report show area, timing and power as zeros. I
cannot get any analysis results. Why?

 

[Jerry]

a wild guess, you have some inputs or/and outputs unconnected and the logic
optimizer
sees that you are not using them so it deletes the logic that is attached to
said inputs outputs.
The logic that was driving the deleted logic is no longer needed so it gets
deleted till there is
no logic to delete.

Just a wild guess.


"Li Yijun" <yxl4444@louisiana.edu> wrote in message
news:3EFFAF87.532C72A2@louisiana.edu...

Hello,

I use Synopsys Design Analyzer to read a verilog file. It is complied
successfully. But why the report show area, timing and power as zeros. I
cannot get any analysis results. Why?