Generate find a good solution

O

Olivier Dir

Guest
I have this process,
pState : process(Clk)
begin
if Clk'event and Clk='1' then
if SRst = '1' then
State <= ST_IDLE;
else
case State is
when ST_IDLE =>
if DspTrfAvb = '1' then
State <= ST_TRF2DSP;
elsif DataAbleRam(1) = '1' then
State <= ST_WDATA1;
elsif DataAbleRam(2) = '1' then
State <= ST_WDATA2;
elsif DataAbleRam(3) = '1' then
State <= ST_WDATA3;
elsif DataAbleRam(4) = '1' then
State <= ST_WDATA4;
elsif DataAbleRam(5) = '1' then
State <= ST_WDATA5;
elsif DataAbleRam(6) = '1' then
State <= ST_WDATA6;
elsif DataAbleRam(7) = '1' then
State <= ST_WDATA7;
elsif DataAbleRam(8) = '1' then
State <= ST_WDATA8;
else
State <= ST_IDLE;
end if;
when ST_WDATA1 =>
if RdDataInRamRd(1) = '1' then
State <= ST_DATA1;
else
State <= ST_WDATA1;
end if;
when ST_DATA1 =>
if DataAbleRamRd(1) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA1;
end if;
when ST_WDATA2 =>
if RdDataInRamRd(2) = '1' then
State <= ST_DATA2;
else
State <= ST_WDATA2;
end if;
when ST_DATA2 =>
if DataAbleRamRd(2) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA2;
end if;
when ST_WDATA3 =>
if RdDataInRamRd(3) = '1' then
State <= ST_DATA3;
else
State <= ST_WDATA3;
end if;
when ST_DATA3 =>
if DataAbleRamRd(3) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA3;
end if;
when ST_WDATA4 =>
if RdDataInRamRd(4) = '1' then
State <= ST_DATA4;
else
State <= ST_WDATA4;
end if;
when ST_DATA4 =>
if DataAbleRamRd(4) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA4;
end if;
when ST_WDATA5 =>
if RdDataInRamRd(5) = '1' then
State <= ST_DATA5;
else
State <= ST_WDATA5;
end if;
when ST_DATA5 =>
if DataAbleRamRd(5) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA5;
end if;
when ST_WDATA6 =>
if RdDataInRamRd(6) = '1' then
State <= ST_DATA6;
else
State <= ST_WDATA6;
end if;
when ST_DATA6 =>
if DataAbleRamRd(6) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA6;
end if;
when ST_WDATA7 =>
if RdDataInRamRd(7) = '1' then
State <= ST_DATA7;
else
State <= ST_WDATA7;
end if;
when ST_DATA7 =>
if DataAbleRamRd(7) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA7;
end if;
when ST_WDATA8 =>
if RdDataInRamRd(8) = '1' then
State <= ST_DATA8;
else
State <= ST_WDATA8;
end if;
when ST_DATA8 =>
if DataAbleRamRd(8) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA8;
end if;
----
end case;
end if;
end if;
end process;

what is the best syntax ?

thank for advance
Olivier
 
On 11/28/2014 10:24 AM, Olivier Dir wrote:
I have this process,
pState : process(Clk)
begin
if Clk'event and Clk='1' then
if SRst = '1' then
State <= ST_IDLE;
else
case State is
when ST_IDLE =
if DspTrfAvb = '1' then
State <= ST_TRF2DSP;
elsif DataAbleRam(1) = '1' then
State <= ST_WDATA1;
elsif DataAbleRam(2) = '1' then
State <= ST_WDATA2;
elsif DataAbleRam(3) = '1' then
State <= ST_WDATA3;
elsif DataAbleRam(4) = '1' then
State <= ST_WDATA4;
elsif DataAbleRam(5) = '1' then
State <= ST_WDATA5;
elsif DataAbleRam(6) = '1' then
State <= ST_WDATA6;
elsif DataAbleRam(7) = '1' then
State <= ST_WDATA7;
elsif DataAbleRam(8) = '1' then
State <= ST_WDATA8;
else
State <= ST_IDLE;
end if;
when ST_WDATA1 =
if RdDataInRamRd(1) = '1' then
State <= ST_DATA1;
else
State <= ST_WDATA1;
end if;
when ST_DATA1 =
if DataAbleRamRd(1) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA1;
end if;
when ST_WDATA2 =
if RdDataInRamRd(2) = '1' then
State <= ST_DATA2;
else
State <= ST_WDATA2;
end if;
when ST_DATA2 =
if DataAbleRamRd(2) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA2;
end if;
when ST_WDATA3 =
if RdDataInRamRd(3) = '1' then
State <= ST_DATA3;
else
State <= ST_WDATA3;
end if;
when ST_DATA3 =
if DataAbleRamRd(3) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA3;
end if;
when ST_WDATA4 =
if RdDataInRamRd(4) = '1' then
State <= ST_DATA4;
else
State <= ST_WDATA4;
end if;
when ST_DATA4 =
if DataAbleRamRd(4) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA4;
end if;
when ST_WDATA5 =
if RdDataInRamRd(5) = '1' then
State <= ST_DATA5;
else
State <= ST_WDATA5;
end if;
when ST_DATA5 =
if DataAbleRamRd(5) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA5;
end if;
when ST_WDATA6 =
if RdDataInRamRd(6) = '1' then
State <= ST_DATA6;
else
State <= ST_WDATA6;
end if;
when ST_DATA6 =
if DataAbleRamRd(6) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA6;
end if;
when ST_WDATA7 =
if RdDataInRamRd(7) = '1' then
State <= ST_DATA7;
else
State <= ST_WDATA7;
end if;
when ST_DATA7 =
if DataAbleRamRd(7) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA7;
end if;
when ST_WDATA8 =
if RdDataInRamRd(8) = '1' then
State <= ST_DATA8;
else
State <= ST_WDATA8;
end if;
when ST_DATA8 =
if DataAbleRamRd(8) = '0' then
State <= ST_CHKTXAVB;
else
State <= ST_DATA8;
end if;
----
end case;
end if;
end if;
end process;

what is the best syntax ?

thank for advance
Olivier
Click to expand...

Not clear what you're asking. The only thing I notice is that
your process has a lot of unnecessary else clauses that assign
the state to its current value. This same action is implied by
leaving out the else clause, and doing so makes the whole thing
shorter, and in my opinion easier to read.

The only other observation is that even if you have fully used
all cases, it is often better to pick one and use "default"
instead of the case name. Some synthesizers have an easier time
to optimize code this way.

--
Gabor
 
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