Guest
The webinars are hosted by Aldec as follows: Thursday 26 April:
EU: 3:00 PM â 4:00 PM (CEST) : https://www.aldec.com/en/events/1012
US: 11:00 AM â 12:00 PM (PDT): https://www.aldec.com/en/events/1011
For an FPGA design we all know that the architecture â all the way from the top to the micro architecture â is critical for both the FPGA quality and the development time. It should be obvious to any experienced designer that this also applies to the testbench.
Most FPGA designs are split into stand-alone modules â for instance for each of the FPGA external interfaces. In VHDL these modules are VHDL entities, and they are normally accessed from a CPU via a standardized register interface, which acts as an abstraction layer. This abstraction allows a safe and efficient control of the complete FPGA.
Such an approach should also be used for the verification environment - to simplify the testbench architecture and the control of the interfaces. This way the verification structure will mirror the design structure, allowing the best possible overview, readability, maintainability and reuse.
See full abstract: https://www.aldec.com/en/events/1011
This webinar will show how UVVM is standardising the VHDL testbench architecture and also present some of the most important UVVM extensions sponsored by ESA (the European Space Agency)
EU: 3:00 PM â 4:00 PM (CEST) : https://www.aldec.com/en/events/1012
US: 11:00 AM â 12:00 PM (PDT): https://www.aldec.com/en/events/1011
For an FPGA design we all know that the architecture â all the way from the top to the micro architecture â is critical for both the FPGA quality and the development time. It should be obvious to any experienced designer that this also applies to the testbench.
Most FPGA designs are split into stand-alone modules â for instance for each of the FPGA external interfaces. In VHDL these modules are VHDL entities, and they are normally accessed from a CPU via a standardized register interface, which acts as an abstraction layer. This abstraction allows a safe and efficient control of the complete FPGA.
Such an approach should also be used for the verification environment - to simplify the testbench architecture and the control of the interfaces. This way the verification structure will mirror the design structure, allowing the best possible overview, readability, maintainability and reuse.
See full abstract: https://www.aldec.com/en/events/1011
This webinar will show how UVVM is standardising the VHDL testbench architecture and also present some of the most important UVVM extensions sponsored by ESA (the European Space Agency)