Z
Zhe Hou
Guest
Hi,
Does anybody know of recent developments on VHDL formal models (preferably in proof assistants like Coq or Isabelle)? I could only find references back in 1996 or earlier. I'm more interested in synthesis semantics (for synthesising actual hardware) than event/simulation semantics (which is used by simulation software).
Many thanks.
Zhe
Does anybody know of recent developments on VHDL formal models (preferably in proof assistants like Coq or Isabelle)? I could only find references back in 1996 or earlier. I'm more interested in synthesis semantics (for synthesising actual hardware) than event/simulation semantics (which is used by simulation software).
Many thanks.
Zhe