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On Wednesday, May 6, 2020 at 11:57:04 PM UTC-7, Anssi Saari wrote:
Zack Sheffield writes:

For those of you who do DSP modeling in Python, I\'ve recently released
a package that supports fixed point arithmetic. The existing open
source tools are lackluster and MATLAB doesn\'t nicely fit into our
simulation/testing workflow. Just trying to get the word out for a
higher adoption rate!

Interesting. When I went looking some months ago I found spfpm
(https://pypi.python.org/pypi/spfpm) which was fairly recently
updated. So how does yours compare? At least compatibility seems tighter
for yours as spfpm works with Python 3.3 and later.

My need was mostly for conversion of floats to VHDL sfixed/ufixed
formats for FPGA testing but in the end I didn\'t need it.
* spfpm has support for various transcendental functions (log, sqrt, sin, cos, tan) whereas fixedpoint does not. As an RTL engineer frustrated with the lack of python tools to more closely model VHDL constructs, I opted to not include these, as ieee libraries do not support these operations for fixed point (ufixed, sfixed, signed, unsigned) types.

* fixedpoint offers several methods/functions for resizing bits of an existing object. It appears that to accomplish this with spfpm, a new object must be created (which is expensive).

* fixedpoint is (at least currently) limited to python 3.8 whereas spfpm (as you mentioned) is compatible back to 3.3. Version 3.8 simplified the code base greatly, so I opted to stick with it.

* Unit tests for spfpm cover very few corner cases. Unit tests for fixedpoint in most cases iterate over at least 1024 random values. Bit accuracy for fixedpoint is validated against MATLAB\'s fixed point designer.

* fixedpoint offers several different rounding schemes (convergent, nearest, toward inf, toward -inf, toward 0, away from 0, floor, ceil) and overflow handling schemes (clamp/saturate, wrap).

* fixedpoint has configurable alerts (error, warning, ignore) for overflow, implicit cast errors, and property mismatches (e.g., adding 2 objects with different rounding schemes).

* I can\'t find any documentation on spfpm other than the docstring in the source file. fixedpoint documents most (if not all) aspects at https://fixedpoint.readthedocs.io.

* fixedpoint has rich string formatting support (using f-strings, format function, or the str.format method)

* fixedpoint is typed (if you like that sort of thing).

* Overall, fixedpoint more closely resembles VHDL constructs than spfpm.

Hope this helps!
 
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Anssi Saari

Guest
zack_sheffield@selinc.com writes:

* fixedpoint is (at least currently) limited to python 3.8 whereas
spfpm (as you mentioned) is compatible back to 3.3. Version 3.8
simplified the code base greatly, so I opted to stick with it.
Thanks for the answers! I also like your clear three clause BSD license,
spfpm has a messy PSF license which basically consists of a bunch of
license texts that were bundled with Python itself.

Out of curiousity and as something of a Python enthusiast, what features
in Python 3.8 were so useful for fixedpoint?
 
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On Friday, May 8, 2020 at 2:10:23 AM UTC-7, Anssi Saari wrote:
Out of curiousity and as something of a Python enthusiast, what features
in Python 3.8 were so useful for fixedpoint?
Three main things:

* walrus operator (https://docs.python.org/3/whatsnew/3.8.html#assignment-expressions) allowed combining of lines of code all over the place.
* Positional-only parameters (https://docs.python.org/3/whatsnew/3.8.html#positional-only-parameters) and keyword arguments allowed for built-in error checking of keyword arguments.
* logging calls got a stacklevel keyword argument (https://docs.python.org/3/library/logging.html#logging.Logger.debug), which basically allows me to wrap logging calls in a single method but always point to the line (outside of that method) where I wanted the log to originate from.

These 3 things greatly enhanced readability and reduced SLOC.
 
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Some time ago a link was posted here to a very comprehensive list of soft CPU designs which included LUT counts, clock rates, instructions per clock and a performance metric incorporating all three. I don\'t recall the author\'s name, but it was amazingly complete.

Anyone remember that? Still got the link?

https://opencores.org/projects/up_core_list/summary
Hey, wow, even our ERIC5 is in there! (Unfortunately, they misspelled our homepage... Correct is: www.entner-electronics.com)
 
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On Sunday, June 28, 2020 at 10:56:11 AM UTC-5, thomas....@gmail.com wrote:
Some time ago a link was posted here to a very comprehensive list of soft CPU designs which included LUT counts, clock rates, instructions per clock and a performance metric incorporating all three. I don\'t recall the author\'s name, but it was amazingly complete.

Anyone remember that? Still got the link?

https://opencores.org/projects/up_core_list/summary


Hey, wow, even our ERIC5 is in there! (Unfortunately, they misspelled our homepage... Correct is: www.entner-electronics.com)
Ugh, could use more recent FPGA LUT counts and Fmax for the the Eric5?

Am starting to get comfortable with Vivado. Want to get updated resource usage on newer parts (16nm parts supported by Webpack version of Vivado).
So far Vivado is not inferring block RAMs like ISE did?
Am getting 50-60% better Fmax for Zynq-US+ over Kintex-7 parts.

Jim Brakefield
 
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On Tuesday, June 30, 2020 at 9:15:32 PM UTC-5, jim.br...@ieee.org wrote:
On Sunday, June 28, 2020 at 10:56:11 AM UTC-5, thomas....@gmail.com wrote:
Some time ago a link was posted here to a very comprehensive list of soft CPU designs which included LUT counts, clock rates, instructions per clock and a performance metric incorporating all three. I don\'t recall the author\'s name, but it was amazingly complete.

Anyone remember that? Still got the link?

https://opencores.org/projects/up_core_list/summary


Hey, wow, even our ERIC5 is in there! (Unfortunately, they misspelled our homepage... Correct is: www.entner-electronics.com)

Ugh, could use more recent FPGA LUT counts and Fmax for the the Eric5?

Am starting to get comfortable with Vivado. Want to get updated resource usage on newer parts (16nm parts supported by Webpack version of Vivado).
So far Vivado is not inferring block RAMs like ISE did?
Am getting 50-60% better Fmax for Zynq-US+ over Kintex-7 parts.

Jim Brakefield
Ugh, getting familiar with Vivado:
Truly timing driven place & route: with timing driven synthesis!
Will use LUT RAM instead of block RAM if it is faster.
So will switch to area optimized flow so block RAM is usually preferred to LUT RAM.
 
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On Monday, August 29, 2016 at 10:24:08 AM UTC-4, Tim Regeant wrote:
On 8/28/2016 11:49 AM, Tim Regeant wrote:
Anyone know where I can find this vintage software?

I am looking for the verion 6.10 free with dongle not required.

I think Synario was the one to release the free version.

Used to be at the ftp site ftp://ftp.synario.com but can\'t reach it now.

Thanks for any help you can offer.

Software has been found, thanks.
I would love to know where you found FutureNet 6.10. Thanks!
 
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Hi Russell!
First of all, thank you very much for this amazing tool. It works wonders and is very well coded.
I do have a question and hope you can help me. For my project, I need to have a specific codeword length. My DATA_BITS size can change, as well as \"T\", but I do need a specific N which is 256 (32 bytes). So far I cannot achieve this. For different values of DATA_BITS and T either I get 31 or 33 bytes codeword length, never 32. I guess this has to do with this piece you wrote on the README: \"Note that the number of errors correctable for a given polynomial is sparse. The search function will choose the next highest number of correctable
errors rather than trying to move to the next polynomial.\"

Any advice on how can I work around this?

Thanks again.
Gabriel
 
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El jueves, 6 de febrero de 1997, 5:00:00 (UTC-3), Paulo Dutra escribió:
I\'m assuming that some of your files exceed the DOS naming convention
of (8.3). The Xilinx core tools are still DOS base and therefore are
limited to the 8.3 rule.

ALLAN LIU wrote:

I am using Xilinx\'s Xact Step software 5.2. I ran xmake in a dos session and it gives me the error that it can\'t find the .wir files created by workview office from Viewlogic. I can see the files and they are in the same directory where I ran xmake. Any ideas? Email me an suggestions. Thanks..

-Allan
axliu@cory.eecs.berkeley.edu

--
/ 7\\\'7 Paulo Dutra (paulo@xilinx.com)
\\ \\ ` Xilinx hotline@xilinx.com
/ / 2100 Logic Drive (800) 255-7778
\\_\\/.\\ San Jose, California 95124-3450 USA (408) 879-6797
Hi. you still have the xtact step. ?
do you know where i can download it
thank you
 
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