enum and Vivado...

[David Bridgham]

I\'m clearly failing to understand how enums are supposed to work in
SystemVerilog.

I\'ve created a header file with the enum definition. I `include that
header file in two files that want to use the common definition. Vivado
complains that the values are multiply defined. If I remove the
`include from one of the files, then the enum values aren\'t defined in
that file and Vivado complains that they\'re not defined. The values are
either defined twice or not at all.

It\'s starting to look to me that enums can only be used within a single
file but that would be silly and would dramatically lessen their
usefulness.

Obviously my background is C where of course you put enum definitions in
header files that are included by everyone. How is it supposed to work
in SystemVerilog?

Thanks for any help on this.

Dave

 

[Rick C]

On Friday, June 5, 2020 at 11:34:17 AM UTC-4, David Bridgham wrote:

I\'m clearly failing to understand how enums are supposed to work in
SystemVerilog.

I\'ve created a header file with the enum definition. I `include that
header file in two files that want to use the common definition. Vivado
complains that the values are multiply defined. If I remove the
`include from one of the files, then the enum values aren\'t defined in
that file and Vivado complains that they\'re not defined. The values are
either defined twice or not at all.

It\'s starting to look to me that enums can only be used within a single
file but that would be silly and would dramatically lessen their
usefulness.

Obviously my background is C where of course you put enum definitions in
header files that are included by everyone. How is it supposed to work
in SystemVerilog?

Thanks for any help on this.

Dave

You might try boiling your code down to a minimum example and posting it. You might also try posting this in the Verilog group. It should get more traction there.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[Theo]

David Bridgham <dab@froghouse.org> wrote:

I\'m clearly failing to understand how enums are supposed to work in
SystemVerilog.

I\'ve created a header file with the enum definition. I `include that
header file in two files that want to use the common definition. Vivado
complains that the values are multiply defined. If I remove the
`include from one of the files, then the enum values aren\'t defined in
that file and Vivado complains that they\'re not defined. The values are
either defined twice or not at all.

I think we need to see some code, but to note that:

enum { x, y, z } foo;

is declaring a variable foo, while:

typedef enum { x, y, z } Foo;

is declaring a type.

If you do the former twice I\'d expect conflicts because foo has been
multiple-declared.

Theo

 

[Kevin Neilson]

On Friday, June 5, 2020 at 9:34:17 AM UTC-6, David Bridgham wrote:

I\'m clearly failing to understand how enums are supposed to work in
SystemVerilog.

I\'ve created a header file with the enum definition. I `include that
header file in two files that want to use the common definition. Vivado
complains that the values are multiply defined. If I remove the
`include from one of the files, then the enum values aren\'t defined in
that file and Vivado complains that they\'re not defined. The values are
either defined twice or not at all.

It\'s starting to look to me that enums can only be used within a single
file but that would be silly and would dramatically lessen their
usefulness.

Obviously my background is C where of course you put enum definitions in
header files that are included by everyone. How is it supposed to work
in SystemVerilog?

Thanks for any help on this.

Dave

It might depend where you\'re putting the `include. Is it inside the module declaration?

Since you are using Systemverilog, I would suggest ditching the `include and using packages instead. I don\'t know if it\'s true for C, but in Verilog, precompiler directives are oldschool kludges. You are using Systemverilog, so you can put enum declarations in packages, which is much cleaner.

 

[David Bridgham]

Theo <theom+news@chiark.greenend.org.uk> writes:

I think we need to see some code, but to note that:

enum { x, y, z } foo;

is declaring a variable foo, while:

typedef enum { x, y, z } Foo;

is declaring a type.

If you do the former twice I\'d expect conflicts because foo has been
multiple-declared.

In fact, I\'m doing the latter. I want a typedef but get the multiply
defined error if I include that header file in two files.

I\'ll work on writing up some simplified code that shows the problem. It
seems so simple what I\'m trying to do that this error suggests I\'m
staggeringly confused about how enums or typedefs work. Or maybe
include files.

 

[David Bridgham]

Kevin Neilson <kevin.neilson@xilinx.com> writes:

It might depend where you\'re putting the `include. Is it inside the
module declaration?

It\'s outside the module declaration. I hadn\'t thought about trying to
put it inside the module declaration.

Since you are using Systemverilog, I would suggest ditching the
`include and using packages instead. I don\'t know if it\'s true for C,
but in Verilog, precompiler directives are oldschool kludges. You are
using Systemverilog, so you can put enum declarations in packages,
which is much cleaner.

I haven\'t run across packages, no idea what they are. Mostly I\'m just
edging into SystemVerilog so I could get enums and typedefs. I thought
they\'d make my code a little cleaner than playing games with `define.

 

[Kevin Neilson]

On Friday, June 5, 2020 at 2:49:58 PM UTC-6, David Bridgham wrote:

Kevin Neilson <kevin.neilson@xilinx.com> writes:

It might depend where you\'re putting the `include. Is it inside the
module declaration?

It\'s outside the module declaration. I hadn\'t thought about trying to
put it inside the module declaration.

Since you are using Systemverilog, I would suggest ditching the
`include and using packages instead. I don\'t know if it\'s true for C,
but in Verilog, precompiler directives are oldschool kludges. You are
using Systemverilog, so you can put enum declarations in packages,
which is much cleaner.

I haven\'t run across packages, no idea what they are. Mostly I\'m just
edging into SystemVerilog so I could get enums and typedefs. I thought
they\'d make my code a little cleaner than playing games with `define.

If you were putting the `include outside the module declaration and move it inside, I would think that would fix the problem. If it\'s outside it might apply to all modules compiled after that one.

enums are great, especially for FSM state names, and allow you to see the state name (instead of a number) in a waveform viewer. (There are kludge ways to do this in Verilog-2005, but they are awkward.) I would use Verilog-2009 (Systemverilog) constructs always, but I\'m usually required to stick to 2005 or earlier so as to be compatible with ASIC tools that are expensive but have parsers from the stone age. So I rarely use packages, but I would if I could. It\'s a similar idea to `include, but more sophisticated than a cut-and-paste. You are definitely right to avoid `defines, though. Most `defines can be replaced by parameters, but enums are better than parameters in some cases.

 

[David Bridgham]

Kevin Neilson <kevin.neilson@xilinx.com> writes:

If you were putting the `include outside the module declaration and
move it inside, I would think that would fix the problem. If it\'s
outside it might apply to all modules compiled after that one.

And that\'s the weird difference between C and Verilog that was baffling
me. In C, definitions like that only apply to the file, not once it\'s
defined it applies to all follow-on files too. Very strange.

Moving the `include inside the module definition kind of worked. I mean
it did, but it prevents me from then using the enum or typedef in the
ports coming into and out of that module. I can work around that.

enums are great, especially for FSM state names, and allow you to see
the state name (instead of a number) in a waveform viewer. (There are
kludge ways to do this in Verilog-2005, but they are awkward.) I
would use Verilog-2009 (Systemverilog) constructs always, but I\'m
usually required to stick to 2005 or earlier so as to be compatible
with ASIC tools that are expensive but have parsers from the stone
age. So I rarely use packages, but I would if I could. It\'s a
similar idea to `include, but more sophisticated than a cut-and-paste.
You are definitely right to avoid `defines, though. Most `defines can
be replaced by parameters, but enums are better than parameters in
some cases.

I\'d love to use packages as they look like they do much more of the
right thing. And I tried it with Vivado and it worked just fine. While
I\'m not using ASIC tools, I am also using Icarus Verilog for fast
turn-around testing and it only understands bits and pieces of
SystemVerilog. It can parse (and ignore?) the package declaration but
it can\'t handle the import statement. Sigh.

Anyway, you\'ve put me on the right track. Thanks a lot.