Guest
Hi
I just wanted to know if people use systemc instead VHDL. Systemc can be used for cycle accurate simulation, where it can replace RTL. In this mode
test-benches will usually take advantage of C++ and SCV (for writing constraints).
For big designs where RTL completion takes a lot of time, systemc can be used
for LT or AT simulations ( Loosely Timed, Approximately Timed TLM).
Pini
I just wanted to know if people use systemc instead VHDL. Systemc can be used for cycle accurate simulation, where it can replace RTL. In this mode
test-benches will usually take advantage of C++ and SCV (for writing constraints).
For big designs where RTL completion takes a lot of time, systemc can be used
for LT or AT simulations ( Loosely Timed, Approximately Timed TLM).
Pini