Do you think my code is right on DFF with only variable usag

[fl]

Hi,

I see a question online:

how will u write d ff using variables alone

Below is my VHDL code. Because I do not see any specialties in the code,
I suspect that the code is not it is supposed to be.

What is your opinion on the question?


Thanks,


...................
process(CLR,PRE,CLK) --process with sensitivity list.
variable v_d: std_ulogic := '0';
begin

if (CLR = '1') then --Asynchronous clear input
v_d := '0';
else
if(PRE = '1') then --Asynchronous set input
v_d := '1';
else
if ( CE = '1' and falling_edge(CLK) ) then
v_d := '1';
end if;
end if;
end if;
Q <= v_d;
end process;

 

[KJ]

On Thursday, May 21, 2015 at 7:15:11 AM UTC-4, fl wrote:

Hi,

I see a question online:

how will u write d ff using variables alone

Below is my VHDL code. Because I do not see any specialties in the code,
I suspect that the code is not it is supposed to be.

What is your opinion on the question?

1. You didn't actually use the 'D' input of the flip flop. Corrected code is:

if ( CE = '1' and falling_edge(CLK) ) then
v_d := d; -- OLD v_d := '1';
end if;

2. The assignment "Q <= v_d" makes use of a signal which violates your statement of "using variables alone". Obviously in order to be able to use the output of the flip flop outside of the process you have to use a signal, so what exactly is your point of trying to have a process that supposedly only uses variables (but doesn't).

Kevin Jennings