DDS questions...

[Gerhard Hoffmann]

Am 07.08.22 um 22:37 schrieb Gerhard Hoffmann:

The essence of the Collins paper is that it takes several
pairs of (filter + amplifier) in cascade, not a dumb comparator.

I forgot:

The filters have to be tighter from stage to stage.
There is an optimum.
In the time nuts archives, there is a spreadsheet
that computes the number of stages, gain per stage
and bandwidth.

> Gerhard

 

[John Larkin]

On Sun, 7 Aug 2022 22:37:41 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:

Am 07.08.22 um 21:53 schrieb John Larkin:
On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de
wrote:

Am 07.08.22 um 19:57 schrieb John Larkin:


My question was, why make a sine wave if the final result is a digital
clock?

You can get by with a counter if you are happy with an exact subharmonic
of the clock source.

Trying to build a DDS without a sine table is like shooting
oneself into both feet and then enjoying the feeling as the
proud winner of the filtering wheelchair championchip.

What advantage does a sine table have over making a sawtooth directly
from the MSBs of the phase accumulator? The sine conversion just adds
errors, seems to me.

Near the zero crossing, the filter can\'t tell them apart. The
comparator isn\'t very smart.

A sine is nowhere steeper than at the zero crossing.
The essence of the Collins paper is that it takes several
pairs of (filter + amplifier) in cascade, not a dumb comparator.

Talking of comparators, I just got quite disappointing results
from an ADCMP580, CML.

~70 ps rise and fall time, should be half of that, typ.

rising edge, falling edge is abt. the same:

https://www.flickr.com/photos/137684711@N07/52270474769/in/dateposted-public/

You are signal averaging. Could the problem be jitter?

entire cycle:

https://www.flickr.com/photos/137684711@N07/52269244147/in/dateposted-public/



Gerhard

My inventory report includes the 580, with the note DECIDED TO NOT
USE PART. I can\'t remember why. We do use the 582.



--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[Lasse Langwadt Christensen]

søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:

On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:
sųndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

That has problems too.

We were thinking that you could gain-up and clip the sine wave to
increase the zero-cross slope. The logical end of that is to make a
trapezoid with a steep rise.

keep decreasing the rise time and you get back to a squarewave
a sine is probably some kind of optimum

The DAC lsb increments rarely at low frequencies, so magically include
some lower phase accumulator bits to effectively increase the DAC
sample rate on that steep slope. Digitally interpolate.

but if the DAC can\'t run any faster or have any more bits, how?

 

[John Miles, KE5FX]

On Sunday, August 7, 2022 at 1:52:07 PM UTC-7, John Larkin wrote:

The DAC lsb increments rarely at low frequencies, so magically include
some lower phase accumulator bits to effectively increase the DAC
sample rate on that steep slope. Digitally interpolate.

That\'s actually a good way to visualize the problem. You don\'t care
about the peak, you care about the zero crossings. At frequencies
where the LSBs toggle less often, the resulting phase error will corrupt
the zero crossing points at low offset frequencies. You can\'t fix this
with a filter, only with a DAC.

Try it and you\'ll see (as I did, back when the HI5731 DAC was the SotA
and I didn\'t have one in the parts drawer.) The ugliness of the output
that you will get from the MSB by itself is hard to exaggerate.

-- john, KE5FX

 

[John Larkin]

On Sun, 7 Aug 2022 14:53:39 -0700 (PDT), \"John Miles, KE5FX\"
<jmiles@gmail.com> wrote:

On Sunday, August 7, 2022 at 1:52:07 PM UTC-7, John Larkin wrote:
The DAC lsb increments rarely at low frequencies, so magically include
some lower phase accumulator bits to effectively increase the DAC
sample rate on that steep slope. Digitally interpolate.

That\'s actually a good way to visualize the problem. You don\'t care
about the peak, you care about the zero crossings. At frequencies
where the LSBs toggle less often, the resulting phase error will corrupt
the zero crossing points at low offset frequencies. You can\'t fix this
with a filter, only with a DAC.

Try it and you\'ll see (as I did, back when the HI5731 DAC was the SotA
and I didn\'t have one in the parts drawer.) The ugliness of the output
that you will get from the MSB by itself is hard to exaggerate.

-- john, KE5FX

Anywhere near Nyquist, the DAC output is ghastly. It looks like random
noise, hard to see anything coherent on a scope. But after a good
filter, it becomes a beautiful sine wave.

If you flip the impulse response of a lowpass filter (like doing
convolution) it shows how much the filter remembers, how much it looks
back in time. My proposed sawtooth has a sharp jump that a sine wave
doesn\'t. If the filter has forgotten the jump, the sawtooth is ideal.
If not, the soft history of a sine wave might be better.

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[whit3rd]

On Sunday, August 7, 2022 at 3:29:03 PM UTC-7, John Larkin wrote:

... My proposed sawtooth has a sharp jump that a sine wave
doesn\'t. If the filter has forgotten the jump, the sawtooth is ideal.
If not, the soft history of a sine wave might be better.

But, doesn\'t the \'sharp jump\' have synchrony with a clock edge?
And, doesn\'t a sharp jump, like a clock, require a big impulse of current out of your filtered
power supply? The sinewave is cleaner to drive, and less insistent on knowledge
of dispersion in the dielectric materials. As others have pointed out,
that\'s why wiring time delays are precise only with sinewaves: no hook there.

 

[John Larkin]

On Sun, 7 Aug 2022 15:36:23 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

On Sunday, August 7, 2022 at 3:29:03 PM UTC-7, John Larkin wrote:

... My proposed sawtooth has a sharp jump that a sine wave
doesn\'t. If the filter has forgotten the jump, the sawtooth is ideal.
If not, the soft history of a sine wave might be better.

But, doesn\'t the \'sharp jump\' have synchrony with a clock edge?

Sure. The dds DAC is clocked by the main clock. Every dac output point
is clocked.

And, doesn\'t a sharp jump, like a clock, require a big impulse of current out of your filtered
power supply? The sinewave is cleaner to drive, and less insistent on knowledge
of dispersion in the dielectric materials. As others have pointed out,
that\'s why wiring time delays are precise only with sinewaves: no hook there.

We are in the picosecond timing business. We use sub-ns edges for
clocks and events. We don\'t use sine waves!

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[Ricky]

On Sunday, August 7, 2022 at 4:52:07 PM UTC-4, John Larkin wrote:

On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:
sųndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

That has problems too.

We were thinking that you could gain-up and clip the sine wave to
increase the zero-cross slope. The logical end of that is to make a
trapezoid with a steep rise.

Making the trapezoid from the NCO output is not the same as making a sine wave and filtering. The \"logical end\" of that is actually generating a square wave with all the attendant jitter. So the trapezoid would increase the jitter and be harder to filter than the sine wave.

The DAC lsb increments rarely at low frequencies, so magically include
some lower phase accumulator bits to effectively increase the DAC
sample rate on that steep slope. Digitally interpolate.

You must have enough phase bits to prevent phase noise since this produces, hard to filter (meaning impossible) close in spurs.

One way to get low trigger rates, which we do now, is synthesize an
octave or so at the high end of the DDS and divide after the
comparator. That has uglies if the DDS is slow to program, like an SPI
interface. It\'s not so awful if we make our own DDS in an FPGA, so we
can change the DDS frequency and the divisor (almost) simultaneously.

Yup. Is there some reason you can\'t piggy back on the SPI protocol to add bits to control your octave divider?

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

 

[John Miles, KE5FX]

On Sunday, August 7, 2022 at 3:55:46 PM UTC-7, John Larkin wrote:

We are in the picosecond timing business. We use sub-ns edges for
clocks and events. We don\'t use sine waves!

Around here, picosecond-level errors mean that somebody (i.e., me)
is going to have a bad day at the (proverbial) office.

-- john, KE5FX

 

[John Larkin]

On Sun, 7 Aug 2022 15:36:23 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

On Sunday, August 7, 2022 at 3:29:03 PM UTC-7, John Larkin wrote:

... My proposed sawtooth has a sharp jump that a sine wave
doesn\'t. If the filter has forgotten the jump, the sawtooth is ideal.
If not, the soft history of a sine wave might be better.

But, doesn\'t the \'sharp jump\' have synchrony with a clock edge?
And, doesn\'t a sharp jump, like a clock, require a big impulse of current out of your filtered
power supply? The sinewave is cleaner to drive, and less insistent on knowledge
of dispersion in the dielectric materials. As others have pointed out,
that\'s why wiring time delays are precise only with sinewaves: no hook there.

The power supply isn\'t an issue. All sorts of things are whacking the
power supply.

But if we make a sawtooth that ramps from -V to +V, and we filter
that, the big negative spike happens at the input clock rate, so
wobbles the zero crossing and makes jitter. The filter isn\'t perfect
so doesn\'t forget the big negative step in half the sawtooth time.

So move the comparator trigger level up, to 0.9V instead of zero, and
that gives the filter almost twice the time to forget.



--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[John Larkin]

On Sun, 7 Aug 2022 16:50:40 -0700 (PDT), \"John Miles, KE5FX\"
<jmiles@gmail.com> wrote:

On Sunday, August 7, 2022 at 3:55:46 PM UTC-7, John Larkin wrote:
We are in the picosecond timing business. We use sub-ns edges for
clocks and events. We don\'t use sine waves!

Around here, picosecond-level errors mean that somebody (i.e., me)
is going to have a bad day at the (proverbial) office.

-- john, KE5FX

We swept two edges across one another and poked them into the data and
clock of an NB7V52 GigaComm flipflop.

https://www.dropbox.com/s/qahpb8uh1xr53vj/NB7_Steps.jpg?raw=1

We saw about 60 fS RMS jitter, which is the flop and the circuits that
generated the time sweep.

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[Clifford Heath]

On 7/8/22 23:55, John Larkin wrote:

To make a programmable-frequency clock, the usual DDS chip has
A frequency-set register, N=32 or 48 bits or something
which adds, every clock, to a phase accumulator
M most-significant bits of that goes into a sine lookup table
Which clocks D bits into a DAC
Which drives a lowpass filter and a comparator.

Why do the sine lookup?

Common DDS evaluation boards come with a 7th-order filter at about 40%
of the clock rate, so for a 180MHz AD9851 at 180MHz the filter is around
72MHz. That produces reasonable signals between 30-70Mhz, but if you
want to produce 1MHz, the signal turns into a staircase roughly
following the sine curve. (the 40% is a compromise to allow the filter
to remove most of the first DDS image, which will be at 60%)

If they started with a triangle wave (as you can get from a cheap AD9834
for example) it would still be a staircased triangle - the filter
softens the staircase steps but doesn\'t do anything to make the signal
look like a sine wave. You\'d need a different filer for that.

Clifford Heath

 

[whit3rd]

On Sunday, August 7, 2022 at 3:55:46 PM UTC-7, John Larkin wrote:

On Sun, 7 Aug 2022 15:36:23 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 3:29:03 PM UTC-7, John Larkin wrote:

... My proposed sawtooth has a sharp jump that a sine wave
doesn\'t. If the filter has forgotten the jump, the sawtooth is ideal.
If not, the soft history of a sine wave might be better.

But, doesn\'t the \'sharp jump\' have synchrony with a clock edge?

Sure. The dds DAC is clocked by the main clock. Every dac output point
is clocked.

A post-filter sinewave\'s zero crossings are NOT clocked, though, so can be asynchronous.
The \'filter\' has a Q of maybe 100, gives the sinewave\'s stability a couple of extra
digits worth of jitter suppression. Such a filter, with a transient rather than a
single-frequency drive, depends on response over ALL the harmonics that
make up that slope. Self-resonance of inductors makes the high harmonics
hard to predict (and other broadband component issues apply to other cases).

Folk with serious timing issues can use LC filters with superconductors... and
regulate the tank temperature with helium boiloff pressure gages.

 

[Clifford Heath]

On 8/8/22 05:53, John Larkin wrote:

On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de
wrote:

Am 07.08.22 um 19:57 schrieb John Larkin:


My question was, why make a sine wave if the final result is a digital
clock?

You can get by with a counter if you are happy with an exact subharmonic
of the clock source.

Trying to build a DDS without a sine table is like shooting
oneself into both feet and then enjoying the feeling as the
proud winner of the filtering wheelchair championchip.

What advantage does a sine table have over making a sawtooth directly
from the MSBs of the phase accumulator? The sine conversion just adds
errors, seems to me.

The filter adds back in some of what you would have got by increasing
the number of MSBs fed to a sine lookup table (and more amplitude steps,
maybe).

Two adjacent zero-crossings will occur at a different time in the filter
output compared to its input, unless the clock is a harmonic of your
output frequency.

 

[Ricky]

On Sunday, August 7, 2022 at 8:48:17 PM UTC-4, John Larkin wrote:

On Sun, 7 Aug 2022 15:36:23 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 3:29:03 PM UTC-7, John Larkin wrote:

... My proposed sawtooth has a sharp jump that a sine wave
doesn\'t. If the filter has forgotten the jump, the sawtooth is ideal.
If not, the soft history of a sine wave might be better.

But, doesn\'t the \'sharp jump\' have synchrony with a clock edge?
And, doesn\'t a sharp jump, like a clock, require a big impulse of current out of your filtered
power supply? The sinewave is cleaner to drive, and less insistent on knowledge
of dispersion in the dielectric materials. As others have pointed out,
that\'s why wiring time delays are precise only with sinewaves: no hook there.
The power supply isn\'t an issue. All sorts of things are whacking the
power supply.

But if we make a sawtooth that ramps from -V to +V, and we filter
that, the big negative spike happens at the input clock rate, so
wobbles the zero crossing and makes jitter. The filter isn\'t perfect
so doesn\'t forget the big negative step in half the sawtooth time.

So move the comparator trigger level up, to 0.9V instead of zero, and
that gives the filter almost twice the time to forget.

You don\'t want the filter to forget. The point of the filter is to integrate the timing, average to put it another way. You want it to remember the zero crossings so as to remove as much jitter as possible. You keep talking like what is important is only the careful construction of the current edge of the waveform.

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209

 

[Phil Hobbs]

Gerhard Hoffmann wrote:

Am 07.08.22 um 22:37 schrieb Gerhard Hoffmann:

The essence of the Collins paper is that it takes several
pairs of (filter + amplifier) in cascade, not a dumb comparator.

I forgot:

The filters have to be tighter from stage to stage.
There is an optimum.
In the time nuts archives, there is a spreadsheet
that computes the number of stages, gain per stage
and bandwidth.

Gerhard

I suspect the minimum will vary depending on the criteria. You don\'t
gain much by making the filters so narrow that their parametric drifts
start going all over the place. Lots of things get worse by factors of Q.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Mike Monett]

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

Gerhard Hoffmann wrote:
Am 07.08.22 um 22:37 schrieb Gerhard Hoffmann:

The essence of the Collins paper is that it takes several pairs of
(filter + amplifier) in cascade, not a dumb comparator.

I forgot:

The filters have to be tighter from stage to stage.
There is an optimum.
In the time nuts archives, there is a spreadsheet
that computes the number of stages, gain per stage
and bandwidth.

Gerhard


I suspect the minimum will vary depending on the criteria. You don\'t
gain much by making the filters so narrow that their parametric drifts
start going all over the place. Lots of things get worse by factors of
Q.

Cheers

Phil Hobbs

I never bought into the Collins theory. A bit of fiddling in LTspice and
simple pen-and-paper work shows the last stage is all that matters.

Other attempts to improve on Collins fail in the first paragraphs. For
example, Attila Kinali assumes the limiter has hysteresis. As far as I
know, no limiter worth it\'s salt has hysteresis. See

http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf

It is referenced in

https://www.mail-archive.com/time-nuts@lists.febo.com/msg08534.html

One problem with high gain limiters is ground bounce. This can cause
feedback to the input stage that causes effects similar to hysteresis, or
even oscillations. Many limiters restrict the minimum slew rate, or even
do not specify the performance in a band around zero. This means the
circuit cannot be used at low frequencies or even DC.

I believe it was Bruce Griffiths who championed low gain stages driving
back-to-back diodes between stages. This would alleviate the ground bounce
problem and allow slew rates down to DC.





--
MRM

 

[Mike Monett]

Mike Monett <spamme@not.com> wrote:

[...]

One problem with high gain limiters is ground bounce. This can cause
feedback to the input stage that causes effects similar to hysteresis,
or even oscillations. Many limiters restrict the minimum slew rate, or
even do not specify the performance in a band around zero. This means
the circuit cannot be used at low frequencies or even DC.

It took a while to find the right google-fu, but I finally found an
example:

MINIMUM INPUT SLEW RATE REQUIREMENT
As with many high speed comparators, a minimum slew rate
requirement must be met to ensure that the device does not
oscillate as the input signal crosses the threshold. This oscil-
lation is due in part to the high input bandwidth of the comparator
and the feedback parasitics inherent in the package. A
minimum slew rate of 50 V/µs must ensure clean output
transitions from the ADCMP580/ADCMP581/ADCMP582
family of comparators.

https://www.analog.com/media/en/technical-documentation/data-sheets/ADCMP58
0_581_582.pdf

I believe it was Bruce Griffiths who championed low gain stages driving
back-to-back diodes between stages. This would alleviate the ground
bounce problem and allow slew rates down to DC.

--
MRM

 

[Phil Hobbs]

Mike Monett wrote:

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

Gerhard Hoffmann wrote:
Am 07.08.22 um 22:37 schrieb Gerhard Hoffmann:

The essence of the Collins paper is that it takes several pairs of
(filter + amplifier) in cascade, not a dumb comparator.

I forgot:

The filters have to be tighter from stage to stage.
There is an optimum.
In the time nuts archives, there is a spreadsheet
that computes the number of stages, gain per stage
and bandwidth.

Gerhard


I suspect the minimum will vary depending on the criteria. You don\'t
gain much by making the filters so narrow that their parametric drifts
start going all over the place. Lots of things get worse by factors of
Q.

Cheers

Phil Hobbs

I never bought into the Collins theory. A bit of fiddling in LTspice and
simple pen-and-paper work shows the last stage is all that matters.

Other attempts to improve on Collins fail in the first paragraphs. For
example, Attila Kinali assumes the limiter has hysteresis. As far as I
know, no limiter worth it\'s salt has hysteresis. See

http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf

It is referenced in

https://www.mail-archive.com/time-nuts@lists.febo.com/msg08534.html

One problem with high gain limiters is ground bounce. This can cause
feedback to the input stage that causes effects similar to hysteresis, or
even oscillations. Many limiters restrict the minimum slew rate, or even
do not specify the performance in a band around zero. This means the
circuit cannot be used at low frequencies or even DC.

I believe it was Bruce Griffiths who championed low gain stages driving
back-to-back diodes between stages. This would alleviate the ground bounce
problem and allow slew rates down to DC.

Just using fully differential stages (a la ECL) fixes the ground bounce
problem pretty well.

The wideband noise both adds and intermodulates with the desired signal,
causing phase noise. In the high-SNR limit, the RMS phase noise
deviation (rad/sqrt(Hz)) due to additive noise can be found from the
small-angle approximation:

<delta phi> = 1/sqrt(2 * SNR ).

As long as the intermodulation is small, I agree that the last stage is
most of what matters, but not 100%.

Noise intermodulation will shift not just the zero crossings, but also
the times when the amplifier goes in and out of clipping. The next
filter will turn that into a zero-crossing shift.


Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Phil Hobbs]

Phil Hobbs wrote:

Mike Monett wrote:
Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

Gerhard Hoffmann wrote:
Am 07.08.22 um 22:37 schrieb Gerhard Hoffmann:

The essence of the Collins paper is that it takes several pairs of
(filter + amplifier) in cascade, not a dumb comparator.

I forgot:

The filters have to be tighter from stage to stage.
There is an optimum.
In the time nuts archives, there is a spreadsheet
that computes the number of stages, gain per stage
and bandwidth.

Gerhard


I suspect the minimum will vary depending on the criteria.  You don\'t
gain much by making the filters so narrow that their parametric drifts
start going all over the place.  Lots of things get worse by factors of
Q.

Cheers

Phil Hobbs

I never bought into the Collins theory. A bit of fiddling in LTspice and
simple pen-and-paper work shows the last stage is all that matters.

Other attempts to improve on Collins fail in the first paragraphs. For
example, Attila Kinali assumes the limiter has hysteresis. As far as I
know, no limiter worth it\'s salt has hysteresis. See

http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf

It is referenced in

https://www.mail-archive.com/time-nuts@lists.febo.com/msg08534.html

One problem with high gain limiters is ground bounce. This can cause
feedback to the input stage that causes effects similar to hysteresis, or
even oscillations. Many limiters restrict the minimum slew rate, or even
do not specify the performance in a band around zero. This means the
circuit cannot be used at low frequencies or even DC.

I believe it was Bruce Griffiths who championed low gain stages driving
back-to-back diodes between stages. This would alleviate the ground
bounce
problem and allow slew rates down to DC.

Just using fully differential stages (a la ECL) fixes the ground bounce
problem pretty well.

The wideband noise both adds and intermodulates with the desired signal,
causing phase noise.  In the high-SNR limit, the RMS phase noise
deviation (rad/sqrt(Hz)) due to additive noise can be found from the
small-angle approximation:

delta phi> = 1/sqrt(2 * SNR ).

As long as the intermodulation is small, I agree that the last stage is
most of what matters, but not 100%.

Noise intermodulation will shift not just the zero crossings, but also
the times when the amplifier goes in and out of clipping. The next
filter will turn that into a zero-crossing shift.

I should add that it\'s important that the limiter be fully differential,
because otherwise you get a bunch of AM-PM conversion.

It\'s also quite feasible to mix down, limit, filter, and mix back up
again. With ideal mixers, this reduces the limiter\'s phase noise power
by a factor

(f_RF/f_IF)**2.

The LO doesn\'t have to be as stable as the desired signal, because its
phase gets subtracted and then added again.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com