R
Rick C
Guest
Sometimes I think they just wanted to mess with people when they designed VHDL. I recall some long ago conversations with one of the guys who helped design VHDL and while he understood the language well, he understood it the same way a newly hired legal associate understands the law. He knew most of the rules, but didn\'t understand how to usefully apply them to do what needed to be done. That\'s what senior partners are for. More recently it seems like they\'ve changed VHDL in ways that make it much more usable, but not always. Sometime there are things that seem like they should work, but just don\'t.
So my most recent issue is this statement...
Sound_Run <= Alarm_Src ?/= (others => \'0\');
The compiler complains that it doesn\'t understand what size the aggregate should be. Is that because while Alarm_Src is well defined, the comparison operator can accept many different operand widths and the tool can\'t see across the operator???
Alarm_Src is defined as Alarm_Type which is defined
subtype Alarm_Type is unsigned (Technical_Sel downto Tidal_Vol_Sel);
Where the two values in the range are integer constants.
This works...
Sound_Run <= Alarm_Src ?/= (Alarm_Src\'range => \'0\');
I should understand this, but I don\'t.
--
Rick C.
- Get 1,000 miles of free Supercharging
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So my most recent issue is this statement...
Sound_Run <= Alarm_Src ?/= (others => \'0\');
The compiler complains that it doesn\'t understand what size the aggregate should be. Is that because while Alarm_Src is well defined, the comparison operator can accept many different operand widths and the tool can\'t see across the operator???
Alarm_Src is defined as Alarm_Type which is defined
subtype Alarm_Type is unsigned (Technical_Sel downto Tidal_Vol_Sel);
Where the two values in the range are integer constants.
This works...
Sound_Run <= Alarm_Src ?/= (Alarm_Src\'range => \'0\');
I should understand this, but I don\'t.
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209