Could you explain this 'assert' description?

[fl]

Hi,

I learn 'assert' on this link:



http://www.ics.uci.edu/~jmoorkan/vhdlref/assert.html


I don't understand what this passage talks about:

"If the message clause is ommited, a default message is output. The severity
level and the name of the design unit containing the relevant assert
statement may also be output"


For this example line:

assert not OVERFLOW) report "Accumulator overflowed" severity failure;


"If the message clause is ommited" means remove "report "Accumulator
overflowed" severity failure;"?


What is your opinion on this?

Thanks,

 

[rickman]

On 9/29/2015 8:20 PM, fl wrote:

Hi,

I learn 'assert' on this link:



http://www.ics.uci.edu/~jmoorkan/vhdlref/assert.html


I don't understand what this passage talks about:

"If the message clause is ommited, a default message is output. The severity
level and the name of the design unit containing the relevant assert
statement may also be output"


For this example line:

assert not OVERFLOW) report "Accumulator overflowed" severity failure;


"If the message clause is ommited" means remove "report "Accumulator
overflowed" severity failure;"?

Yes, they are saying if you omit the report it will still print a
default report with basic info like the line number, severity level and
time. I don't know what is "required" by VHDL in this default report,
but this is what I have seen simulators do. In fact, the default report
is made even if you indicate a report. Your report is just added to the
default. Try it, you'll see what your tool does.

--

Rick

 

On Wednesday, September 30, 2015 at 3:20:42 AM UTC+3, fl wrote:

Hi,

I learn 'assert' on this link:



http://www.ics.uci.edu/~jmoorkan/vhdlref/assert.html


I don't understand what this passage talks about:

"If the message clause is ommited, a default message is output. The severity
level and the name of the design unit containing the relevant assert
statement may also be output"


For this example line:

assert not OVERFLOW) report "Accumulator overflowed" severity failure;


"If the message clause is ommited" means remove "report "Accumulator
overflowed" severity failure;"?


What is your opinion on this?

Thanks,

The assert statement of VHDL, can be used for simulation stop. This can be in a simple case like just a normal simulation end or a fatal error detection, by the verification test-bench.
2.If the simulation is let run after a fatal error occurs, the debug time may become longer in order to isolate the exact point of failure. While this is obvious, in some cases this rule is ignored. Typical example follows.
3.The simulation stop is done using the VHDL assert statement.


examples are at
http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_stop_on_error.html
http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_test_ctrl_process.html

 

[KJ]

On Tuesday, September 29, 2015 at 8:20:42 PM UTC-4, fl wrote:

Hi,


I don't understand what this passage talks about:

"If the message clause is ommited, a default message is output. The severity
level and the name of the design unit containing the relevant assert
statement may also be output"

The line of code in file D:/Projects/Test.vhd
assert 1 < 0 severity ERROR;
Will produce the following output in Modelsim
# ** Error: Assertion violation.
# Time: 0 ns Iteration: 0 Process: /tb_ulpi_link/line__252 File: D:/Projects/Test.vhd

Kevin