Components in if-else statement...

T

tushar sharma

Guest
I am trying to make a cube computation circuit using Vedic Algorithms.
The code is as follows:
--------------MAIN FILE-------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.ALL;
entity major_8_bit is

port(
N: in std_logic_vector(7 downto 0);
Result: out std_logic_vector(23 downto 0));


end major_8_bit;

architecture RTL of major_8_bit is

component compare
port( N: in std_logic_vector(7 downto 0);
enable: out std_logic);
end component;


component cubeComputation8bit_YES
port(
N: in std_logic_vector(7 downto 0);
Result: out std_logic_vector(23 downto 0));
end component;

component cubeComputation8bit_NO
port(
N: in std_logic_vector(7 downto 0);
Result: out std_logic_vector(24 downto 0));
--to concatenate the carry bit generated from 24bit BA at the 24th index (starting from 1)
end component;
--signals
signal R: std_logic_vector( 7 downto 0);
signal R2: std_logic_vector (7 downto 0):=\"00001111\";
signal ResultNo: std_logic_vector( 24 downto 0);
signal EnableSignal: std_logic;
begin
R <= 100000000 - N;
--enable <= EnableSignal;

Comp: compare port map( N, EnableSignal);


YesCase: if(EnableSignal = \'1\') generate -- YES CASE
CP1: cubeComputation8bit_YES port map (N,Result);
end generate YesCase;
NoCase: if(EnableSignal = \'0\') generate
CP2: cubeComputation8bit_NO port map(N=>N,Result=> ResultNo);
end generate NoCase;
end;
*********************
There is no syntax error being reported, but the code is not simulating because of the components used in the if-else statement (Saw this method on stackoverflow)
The two components cubeComputation8bit_Yes and cubeComputation8bit_NO are working correctly independently. But not when put together this way.

Any help will be highly appreciated.
Regards.
 

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