Can you use a function to populate a ROM?

Hi all,

I'm building a quarter wave lookup table for sin/cos.

I know in VHDL, that it is possible in design rtl to write a behavioral function and then reference that function to set the values of a ROM.

Is that possible in verilog? If so, how might I go about doing it?

If it's not possible, are there any alternative ways I could use behavioral calculations to initialize my lookup table without pre-building with .hex files or scripts?

The idea is to make the whole thing parameterizable.

Thanks,
Stephen

 

[Kevin Neilson]

On Monday, January 13, 2020 at 5:03:42 PM UTC-7, silve...@gmail.com wrote:

Hi all,

I'm building a quarter wave lookup table for sin/cos.

I know in VHDL, that it is possible in design rtl to write a behavioral function and then reference that function to set the values of a ROM.

Is that possible in verilog? If so, how might I go about doing it?

If it's not possible, are there any alternative ways I could use behavioral calculations to initialize my lookup table without pre-building with .hex files or scripts?

The idea is to make the whole thing parameterizable.

Thanks,
Stephen

That is possible, but many synthesizers won't do this well or at all. It's probably easier to use a different program to generate a ROM in a case statement or to put data in a file which you can read in using $readmemh. I have used a function to populate a wire or parameter which acts as a ROM. It will probably have to be flattened into a vector:

parameter X = 7; // Some function input
wire [128*8-1:0] tbl = gen_tbl(X); // 128-byte table flattened into vector

....

function [128*8-1:0] gen_tbl
(input integer X); // some parameter
integer ii; // loop variable
begin
for (ii=0; ii<128-1; ii=ii+1)
gen_tbl[ii*8+:8]=$some_function(ii);
end
endfunction