BlockRam @ 333MHz

[Jan Kindt]

Hi all,

I'm using a VIIpro (P30, -5). My data needs to be buffered before
going to the DDR memory. The DDR databus width is 96bit (6 devices),
which generates a 192bit internal databus.. Target clock rate is
166MHz.
Write burst data needs to be supplied out of the buffer, so logically
I nee a 192bit wide buffer... But does anyone has any faith in the
solution of reading a blockram at 333MHz & doubling the datawith in
register ?
I tried it with a very simple design, and I get almost there... here's
the timing report...

Timing Report
************************************************************************************************
Timing constraint: TS_clkrd2x = PERIOD TIMEGRP "clkrd2x" 3.003 nS
HIGH 50.000000 % ;

150 items analyzed, 2 timing errors detected. (2 setup errors, 0 hold
errors)
Minimum period is 3.017ns.
--------------------------------------------------------------------------------
Slack: -0.014ns (requirement - (data path - clock
skew))
Source: ram0/B5.B (RAM)
Destination: ram0/BU42 (FF)
Requirement: 3.003ns
Data Path Delay: 3.017ns (Levels of Logic = 0)
Clock Skew: 0.000ns
Source Clock: clkrd2x_bufgp rising at 0.000ns
Destination Clock: clkrd2x_bufgp rising at 3.003ns
Timing Improvement Wizard
Data Path: ram0/B5.B to ram0/BU42
Location Delay type Delay(ns) Physical
Resource
Logical
Resource(s)
-------------------------------------------------
-------------------
RAMB16_X5Y19.DOB17 Tbcko 1.680 ram0/B5
ram0/B5.B
SLICE_X65Y158.BX net (fanout=1) 1.074 ram0/N849
SLICE_X65Y158.CLK Tdick 0.263 dram<17>
ram0/BU42
-------------------------------------------------
---------------------------
Total 3.017ns (1.943ns logic,
1.074ns route)
(64.4% logic,
35.6% route)
****************************************************************************************************


So the blockram is fast enough, but the routing around it cannot
handle it quite so good.

This exercise was made with only 1 blockram in an empty V2P30. I would
need 12 blockrams at 333MHz if I go for it.. Otherwise, I'll go for
the 24BRAM's at 166MHz.

I'll synthesise the 333MHz clock using a DCM, could the phase shift
save me some picoseconds somewhere ?

So : question ...
1. Anyone has any experience running BRAM at such a speed ?
2. Anyone has any tips, recommendations to get it some faster ?
3. Anyone has any other ideas to get my thing happen...

thanks y'all for your time.
~iolo