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Bit Numbering in Verilog...

T

Tom Szolyga

Guest
I am working on creating a FPGA implementation of a IBM 7000 series CPU. The bits are numbered with bit 0 as the most significant bit and bit n (n bits per word) as the least significant. Verilog seems to want the opposite order: bit 0 is the least significant bit.

Does anyone know or has anyone tried numbering bits the other way around in Verilog?

Thanks,
Tom
 
J

Julio Di Egidio

Guest
On Monday, 18 October 2021 at 20:09:13 UTC+2, tszo...@pacbell.net wrote:
I am working on creating a FPGA implementation of a IBM 7000 series CPU. The bits are numbered with bit 0 as the most significant bit and bit n (n bits per word) as the least significant. Verilog seems to want the opposite order: bit 0 is the least significant bit.

Does anyone know or has anyone tried numbering bits the other way around in Verilog?
There is no such preference in Verilog: dimensions can be [7:0] as well as [0:7], plus you do the wiring...

HTH,

Julio
 
S

siso

Guest
I guess one has to be careful here. Not sure whether a bit slicing is relevant to your question, nevertheless - here is the example:
wire[31: 0] vA; // OK
wire[ 0: 7] vX; //OK
assign vx = vA[0:7]; //this one will yield and error most likely: Reverse part-select index ordering.
You can\'t do reverse slice indexing. The indexes shall follow the order of declaration.
If something of the kind above is required - I don\'t know a better way of doing it, but using explicit assign bit by bit or (of course) in a cycle etc.
Regards
Svilen
 
G

gnuarm.del...@gmail.com

Guest
On Monday, October 18, 2021 at 2:09:13 PM UTC-4, tszo...@pacbell.net wrote:
I am working on creating a FPGA implementation of a IBM 7000 series CPU. The bits are numbered with bit 0 as the most significant bit and bit n (n bits per word) as the least significant. Verilog seems to want the opposite order: bit 0 is the least significant bit.

Does anyone know or has anyone tried numbering bits the other way around in Verilog?
Yes, use VHDL. Bit ordering is user defined in VHDL. The libraries you use are not always general enough to work with reverse bit ordering, but many will work fine.

Can you use the reverse bit ordering for the external interface and use conventional bit ordering for everything internal? I suppose your instruction memory will want to be IBM ordered... which btw, I think you made a typo. It will range [0 to n-1], not [0 to n]. I believe there were some truly deranged companies that used [1 to n] bit ordering.

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