AXI4-Lite, Avalon-MM, UART, I2C and SPI: VHDL BFMs and VVC

UVVM - the new VHDL verification methodology is a very good way to structure your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectures.

UVVM is free and open source, and now a whole set of BFMs and Verification Components are also available - open source and for free. This allows a very fast kick-off for new users of UVVM, and of course a really good start for any VHDL testbench development. They also serve as examples on how users can make their own BFMs and VVCs. In fact - if you have already made your BFM procedures for your proprietary protocol - you can make a VVC for that interface in 15 to 60 minutes.

Spend 5 minutes to read our post
'Advanced VHDL Verification - Made simple - For anyone'
https://www.linkedin.com/pulse/advanced-vhdl-verification-made-simple-anyone-espen-tallaksen?trk=mp-author-card, and see for your self how UVVM will allow far better and more structured testbenches to be implemented far faster than before.
(Includes picture, so can't be posted here)

UVVM is free and open source, and you can use it for anything you like, with no restrictions other than the standard MIT open source license.
UVVM is available from github.com and bitvis.no (released in February 2016).

Note that advanced randomization and coverage is available with UVVM via the included OSVVM or adapted UVVM-OSVVM.

Available BFMs and VVCs (VHDL Verification Components) are:
- AXI4-Lite
- Avalon-MM (Single access so far)
- SBI: Simple Bus Interface (Single cycle, optional ready - very simple bus interface)
- UART
- I2C
- SPI (coming in June)
- GPIO (coming in June)

As UVVM takes off we expect the VHDL community will make more BFMs and VVCs available.

 

[Adrian Byszuk]

Hello Espen,

UVVM looks really nice to me. I've started playing with AXI4Lite BFM and I really like it.

One addition I would like to see is configurable assertion time for BREADY and RREADY signals, in similar way it's possible for *VALID signals (e.g. config.num_w_pipe_stages).

Other than that, do you plan to support Wishbone protocol? It's fairly widespread, especially in open projects.

Thanks,
Adrian

 

Hi Adrian,

Good to hear you like it

Have you tried the VVC variants yet?
Using a VVC is as easy as using a BFM (just add the given VVC target name as the first parameter). The VVC allows a very structured, simple and automatic simultaneous control of multiple interfaces, so you don't have to control different verification processes or entities "manually".

At the moment we have no resources to make these changes, as vacation is coming up and we need to prioritise other features on our UVVM roadmap.
We do hope that the Open Source VHDL community will embrace UVVM and make new and improved VVCs/BFMs available, so maybe this is a great opportunity to get started. (Maybe we should ask for that in a dedicated post...)
Otherwise I guess we could make the AXI4Lite improvements some time in Q3 or Q4, and maybe also a Wishbone classic VVC/BFM, but we need to evaluate our priorities based on our roadmap and user requests.

-Espen