Asynchronous MUTEX IN VHDL

[Charles Effiong]

Hi all, I need help.

1. Does anyone knows a gate level implementation of asynchronous metastability filter for mutex ? I couldn't find a gate level description online.

2. I created a MUTEX using two NAND gate. Interface is as below:

entity ME is
Port (
R1 : in STD_LOGIC;
R2 : in STD_LOGIC;
G1 : out STD_LOGIC;
G2 : out STD_LOGIC);
end ME;

In my testbench, I have something like this:

wait for clock_cycle;
R1 <= '1';
wait for clock_cycle;
R2 <= '1';


After running simulation, the output G1, G2 is 'U' If I change one of R1,R2 to be '0' it works. What could be wrong ?

3. Does anyone knows how to code an asynchronous arbiter that can be used to control a MUX or demux. I'm did the coding but have some problems simulating it.

Any help or reference materials would be appreciated. Thanks

 

[KJ]

On Wednesday, April 1, 2015 at 8:43:57 AM UTC-4, Charles Effiong wrote:

After running simulation, the output G1, G2 is 'U' If I change one of R1,R2 to be '0' it works. What could be wrong ?

It's your code and you haven't posted it so it's your problem to figure out.

3. Does anyone knows how to code an asynchronous arbiter that can be used to control a MUX or demux. I'm did the coding but have some problems simulating it.

Seems pretty simple to me...
if (R1 = '1') then
G1 <= '1';
G2 <= '0';
else
G1 <= '0';
G2 <= R2;
end if;

Kevin Jennings