Assigning present state to output.

[Mohammed A.khader]

Hi all,

I have a State Machine with 6 states (binary encoded).
TYPE state_vector IS (s0,s1,s2,s3,s4,s5);
SIGNAL pstate,nstate : state_vector;

In order to avoid combinational logic after Filp Flops in a moore
model , I want to assign specific binary values so that I could take
o/ps directly from Flip Flops.

what should I do to achieve it ? I know about the Pragma
ENUM_ENCODING, but it is only for sythesis.I want to check design by
simulation. Is there any particular keyword or other means to assign
particular value to states in VHDL.

Later I have the PORT MAP the o/p from Filp Flop (Present state) to
the next module(which is of type std_logic). Hence I need to convert
the SIGNAL pstate (see above signal declaratoin) to type std_logic.
what could be the better way to do this ?

Thanks in Advance.

IDEA always invited !
Mohammed A. Khader

 

[Egbert Molenkamp]

"Mohammed A.khader" <akfami@hotmail.com> schreef in bericht
news:a132b118.0409060042.76c27062@posting.google.com...

Hi all,

I have a State Machine with 6 states (binary encoded).
TYPE state_vector IS (s0,s1,s2,s3,s4,s5);
SIGNAL pstate,nstate : state_vector;

In order to avoid combinational logic after Filp Flops in a moore
model , I want to assign specific binary values so that I could take
o/ps directly from Flip Flops.

If you want the output to be an output of a flipflop you can also assign to
that output signal in the"synchronous part" of the process.
The you will get then automatically a flipflop. Maybe more flipflops then
minimal required for the system.

what should I do to achieve it ? I know about the Pragma
ENUM_ENCODING, but it is only for sythesis.I want to check design by
simulation. Is there any particular keyword or other means to assign
particular value to states in VHDL.

During simulation your type state_vector is not mapped on any code. During
simulation you will see the states s0 .. s5.
If you want to simulate also the coding you could use the following approach

constant s0 : std_logic_vector(2 downto 0):="000";
...
constant s5 : std_logic_vector(2 downto 0):="101";
signal (or variable) state : std_logic_vector(2 downto 0);]
and then the code you have.

Now you have a combination "logical namens (the constants)" and the binary
code.

Later I have the PORT MAP the o/p from Filp Flop (Present state) to
the next module(which is of type std_logic). Hence I need to convert
the SIGNAL pstate (see above signal declaratoin) to type std_logic.
what could be the better way to do this ?

If the next module requires type std_logic(_vector) you have to make the
conversion. You can write a function.
However if the type state is globaly known you can still use s0 .. s5.

Egbert Molenkamp