ASIC costs

[Ken Smith]

Imagine that you have a circuit involving about fast 8 op-amps (LT1224), a
couple of fast comparitors (LT1016), about 10 discrete transistors and
about 8 polse of filtering. How much are we talking to make an ASIC out
this.

If we also have about 500 macrocells worth of CPLD, an 8051 or so and
about 4Meg of fast RAM. All this runs at about 100MHz. Is it cheaper to
make one ASIC or two.


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kensmith@rahul.net forging knowledge

 

[Mike Harrison]

On Wed, 2 Feb 2005 03:39:00 +0000 (UTC), kensmith@green.rahul.net (Ken Smith) wrote:

Imagine that you have a circuit involving about fast 8 op-amps (LT1224), a
couple of fast comparitors (LT1016), about 10 discrete transistors and
about 8 polse of filtering. How much are we talking to make an ASIC out
this.

If we also have about 500 macrocells worth of CPLD, an 8051 or so and
about 4Meg of fast RAM. All this runs at about 100MHz. Is it cheaper to
make one ASIC or two.


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Have you looked at the programmable analog parts from Cypress and Zetex ?

 

[Rene Tschaggelar]

Ken Smith wrote:

Imagine that you have a circuit involving about fast 8 op-amps (LT1224), a
couple of fast comparitors (LT1016), about 10 discrete transistors and
about 8 polse of filtering. How much are we talking to make an ASIC out
this.

If we also have about 500 macrocells worth of CPLD, an 8051 or so and
about 4Meg of fast RAM. All this runs at about 100MHz. Is it cheaper to
make one ASIC or two.

Do the comparators work faster than the clock ?
Is the filter faster than the clock ?
Do you need more dynamic range than say 8 bits ?

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Ken Smith]

In article <tk9101tkrsunl7ss8u7e5sg9epvb4bn4rt@4ax.com>,
Mike Harrison <mike@whitewing.co.uk> wrote:

On Wed, 2 Feb 2005 03:39:00 +0000 (UTC), kensmith@green.rahul.net (Ken
Smith) wrote:

Imagine that you have a circuit involving about fast 8 op-amps (LT1224), a
couple of fast comparitors (LT1016), about 10 discrete transistors and
about 8 polse of filtering. How much are we talking to make an ASIC out
this.

If we also have about 500 macrocells worth of CPLD, an 8051 or so and
about 4Meg of fast RAM. All this runs at about 100MHz. Is it cheaper to
make one ASIC or two.
[....]
Have you looked at the programmable analog parts from Cypress and Zetex ?

Yes but they don't look to be exactly what we need. They may be part of a
multiple chip solution though.

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kensmith@rahul.net forging knowledge

 

[Ken Smith]

In article <4200b408$1@news1.ethz.ch>, Rene Tschaggelar <none@none.net> wrote:
[...]

Do the comparators work faster than the clock ?

The delay through one of them must vary by less than 4nS.

I can't stand any cogging in the comparitor so it must not be synced to
the clock edge unless the clock is very high. (About 10GHz)

Is the filter faster than the clock ?
Yes as things stand it is.

Do you need more dynamic range than say 8 bits ?

Yes, at least 16 bits looks to be needed. It may be more depending on how
the quantization interacts with the rest of the system.

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kensmith@rahul.net forging knowledge

 

[Joerg]

Hello Ken,

Consider Frank's ADC-DSP idea but use a fast and modern DSP with plenty
of floating point horsepower, multiplier, leather seats and the whole
nine yards. No FPGA. It might be able to do the filtering and stuff at
an acceptable prop delay penalty. For cost reasons 4MB RAM might better
be kept outside as an extra chip, at least for the time being.

Regards, Joerg

http://www.analogconsultants.com

 

[Ken Smith]

In article <UHaMd.16$aW6.6@newssvr22.news.prodigy.net>,
Joerg <notthisjoergsch@removethispacbell.net> wrote:

Hello Ken,

Consider Frank's ADC-DSP idea but use a fast and modern DSP with plenty
of floating point horsepower, multiplier, leather seats and the whole
nine yards. No FPGA. It might be able to do the filtering and stuff at
an acceptable prop delay penalty. For cost reasons 4MB RAM might better
be kept outside as an extra chip, at least for the time being.

I think this is coming down to the "find another way" result. It looks
like the ASIC is out of the question. Maintaining an input to output
delay that is stable with a DSP sounds tricky (hmmmm unless).

There can't be any beat between the harmonics of the input and the clock
of the DSP. None = less than 0.0001 degrees RMS of phase jitter in a
500KHz signal. A fixed phase error can be about a degree without too much
trouble.


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kensmith@rahul.net forging knowledge

 

[Tim Shoppa]

None = less than 0.0001 degrees RMS of phase jitter in a
500KHz signal.

That corresponds to 0.55 picoseconds. That's achievable in at least
some domains, but not knowing the real need it's starting to sound like
specsmanship.

Tim.

 

[Ken Smith]

In article <1107537112.301920.73890@f14g2000cwb.googlegroups.com>,
Tim Shoppa <shoppa@trailing-edge.com> wrote:

None = less than 0.0001 degrees RMS of phase jitter in a
500KHz signal.

That corresponds to 0.55 picoseconds. That's achievable in at least
some domains, but not knowing the real need it's starting to sound like
specsmanship.

Remember that this is an RMS jitter (ie: short term) not the absolute
error of the long term drift. The 0.0001 degrees number comes from the
real requirements to match the system performance.

Now: what does "some domains" mean in this context.

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kensmith@rahul.net forging knowledge

 

[Ken Smith]

In article <U8PMd.457$lz5.335@newssvr24.news.prodigy.net>,
Joerg <notthisjoergsch@removethispacbell.net> wrote:
[...]

Plus exactly determining the number of clock cycles it takes to execute.
Should be possible even on newer DSP. We have done that but it was with
the old Analog Devices 2105 processors. These may look like a moped
compared to today's rocket DSPs but one single clock cycle of skew would
have thrown our whole Doppler detection off kilter. It didn't, operated
like clockwork.

Imagine you have a signal at 500.001KHz and you digitize it at 5MHz. When
you digitize, you add distortion products and these will beat with the
5MHz and the waveforms slide past each other. When you are done with the
DSPing, you are going to turn the signal back into analog. At this point
more distortion products get added.

Regards, Joerg

http://www.analogconsultants.com

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kensmith@rahul.net forging knowledge

 

[Ken Smith]

In article <cu070r$ffl$1@lilja.vtt.fi>,
Mikko Kiviranta <Okkim.Atnarivik@iki.fi.invalid> wrote:
[...]

do some searching to find suitable amp blocks. 8051's are often
available as synthesizable cores for most mixed-signal processes.

I can convert from 8051 to equivelent logic.

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kensmith@rahul.net forging knowledge

 

[Tim Shoppa]

Now: what does "some domains" mean in this context.

0.55 picoseconds is a pretty good jitter figure for leading-edge
technology telecom clocks. Typical rise and fall times for these
pulses is of the order a few tens of picoseconds. Trying to do the
same thing for a sine-shaped wave of 500kHz (which is a fall time of
millions of picoseconds) is ludicrous. The noise on your noise on your
noise will make this impossible.

Tim.

 

[Ken Smith]

In article <p6VMd.586$lz5.394@newssvr24.news.prodigy.net>,
Joerg <notthisjoergsch@removethispacbell.net> wrote:
[....]

You'll need all the ADC bits money can buy. 16 bits would be possible at
5MSPS but it'll be expensive, probably above $30 plus lots of housekeeping.

$1000 each would not kill the idea. That would still make the ASIC less
than 25% of the total cost of the current system. A lower price would be
nicer.

Question: Why do you want to integrate this anyway? Space constraints?

This is one part of it.

Cost?

This is not really an issue with the electronics a things stand.

Another reason is to help keep what we are doing a secret. I figure it
will delay the other guys by more than a year. A small time operator
won't have the ability to copy an ASIC.


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[Tim Hubberstey]

Ken Smith wrote:

The problem with the FPGA idea is that the boot up stuff is not stored
right in the chip so it is very insecure.

Xilinx has addressed the security issue in some of their parts by
providing a small area of battery-backed write-only RAM where decryption
keys are stored before the product is shipped. At each boot, the
bitstream is downloaded in encrypted form and decrypted by a built-in
decryption engine in the chip.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com