anti-foldback current limiter...

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Guest
I\'ve finished up the PCB design of my new class-D power amp, so now
the kids have to change the FPGA and ARM code to match. One problem is
current limiting. We have a current shunt on the amp output, but we
don\'t sense the voltage across the load.

We were brainstorming and simulating current limit schemes that we can
implement in the FPGA, which drives the DAC into my amp, and sees the
sensed load current. A hard clipper needs a lot of gain, and the
customer load is unknown, so a high-gain loop might be unstable.

So I was wondering (about 3 AM) how bad a low-gain clipper would be,
when it occurrs to me that a class-D amp has current gain from its
power supply into the load, so we can have a higher current limit at
low voltage out, for instance when the customer shorts our output.
It\'s an anti-foldback current limit in a system that can\'t sense the
output voltage.

This seems to work in an analog model. At any rate, it makes a cool
waveform at Isense. The current limit goes up when the load resistance
goes down. I\'m still trying to get my brain comfortable with that.
More coffee is indicated.

At the extreme implementation of anti-foldback, a graph of current
limit vs output voltage would be really strange, uuuuuu with spikes to
infinity.



Version 4
SHEET 1 1224 724
WIRE 1120 16 432 16
WIRE 432 64 432 16
WIRE -64 80 -128 80
WIRE 0 80 -64 80
WIRE 176 80 80 80
WIRE 288 80 176 80
WIRE 384 80 288 80
WIRE 1072 112 1024 112
WIRE 1120 112 1120 16
WIRE 1120 112 1072 112
WIRE 384 128 352 128
WIRE -128 144 -128 80
WIRE 176 160 176 80
WIRE 352 176 352 128
WIRE 432 176 432 144
WIRE 1120 176 1120 112
WIRE 176 288 176 224
WIRE 272 288 176 288
WIRE 432 288 352 288
WIRE 512 288 432 288
WIRE 672 288 592 288
WIRE 720 288 672 288
WIRE -128 304 -128 224
WIRE 720 352 720 288
WIRE 272 368 256 368
WIRE 304 368 272 368
WIRE 880 368 768 368
WIRE 976 368 880 368
WIRE 1120 368 1120 256
WIRE 1120 368 1056 368
WIRE 304 400 304 368
WIRE 880 400 880 368
WIRE 432 416 432 288
WIRE 432 416 336 416
WIRE 784 416 768 416
WIRE 176 432 176 288
WIRE 272 432 176 432
WIRE 432 448 336 448
WIRE 480 448 432 448
WIRE 496 448 480 448
WIRE 1120 448 1120 368
WIRE 720 464 720 432
WIRE 784 464 784 416
WIRE 784 464 720 464
WIRE -96 480 -128 480
WIRE -80 480 -96 480
WIRE 64 480 32 480
WIRE 80 480 64 480
WIRE 720 496 720 464
WIRE 880 496 880 464
WIRE -128 512 -128 480
WIRE 32 512 32 480
WIRE 272 512 256 512
WIRE 304 512 304 464
WIRE 304 512 272 512
WIRE 432 512 432 448
WIRE -128 640 -128 592
WIRE 32 640 32 592
WIRE 432 640 432 592
WIRE 1120 640 1120 528
FLAG -128 304 0
FLAG 432 640 0
FLAG -128 640 0
FLAG 32 640 0
FLAG -96 480 +5
FLAG 64 480 -5
FLAG 272 512 -5
FLAG 272 368 +5
FLAG 352 176 0
FLAG 432 176 0
FLAG 880 496 0
FLAG 1120 640 0
FLAG 720 496 0
FLAG -64 80 DDS
FLAG 288 80 CLIP
FLAG 480 448 LIM
FLAG 672 288 Isense
FLAG 1072 112 VOUT
SYMBOL res 96 64 R90
WINDOW 0 69 57 VBottom 2
WINDOW 3 74 59 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL diode 160 160 R0
WINDOW 0 -62 30 Left 2
WINDOW 3 -84 62 Left 2
SYMATTR InstName D1
SYMATTR Value 1N914
SYMBOL voltage -128 128 R0
WINDOW 0 37 102 Left 2
WINDOW 3 17 145 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdds
SYMATTR Value SINE(2.5 2.5 1K)
SYMBOL voltage 432 496 R0
WINDOW 0 57 38 Left 2
WINDOW 3 62 70 Left 2
SYMATTR InstName Vlim
SYMATTR Value 2.5
SYMBOL Opamps\\\\UniversalOpamp2 304 432 M0
WINDOW 0 -57 -53 Left 2
SYMATTR InstName U1
SYMBOL res 368 272 R90
WINDOW 0 -38 56 VBottom 2
WINDOW 3 -33 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL res 608 272 R90
WINDOW 0 -40 56 VBottom 2
WINDOW 3 -33 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL voltage -128 496 R0
WINDOW 0 51 37 Left 2
WINDOW 3 55 75 Left 2
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL voltage 32 496 R0
WINDOW 0 60 33 Left 2
WINDOW 3 59 69 Left 2
SYMATTR InstName V4
SYMATTR Value -5
SYMBOL e 432 48 R0
WINDOW 0 51 43 Left 2
WINDOW 3 68 76 Left 2
SYMATTR InstName Eamp
SYMATTR Value 10
SYMBOL res 1104 160 R0
WINDOW 0 -101 36 Left 2
WINDOW 3 -90 74 Left 2
SYMATTR InstName Rload
SYMATTR Value {RL}
SYMBOL res 1104 432 R0
WINDOW 0 -108 64 Left 2
WINDOW 3 -89 93 Left 2
SYMATTR InstName Rshunt
SYMATTR Value 1m
SYMBOL e 720 336 M0
WINDOW 0 74 48 Left 2
WINDOW 3 62 81 Left 2
SYMATTR InstName E2
SYMATTR Value 1000
SYMBOL res 1072 352 R90
WINDOW 0 -41 53 VBottom 2
WINDOW 3 -35 54 VTop 2
SYMATTR InstName R4
SYMATTR Value 1K
SYMBOL cap 864 400 R0
WINDOW 0 51 22 Left 2
WINDOW 3 49 51 Left 2
SYMATTR InstName C1
SYMATTR Value 1n
TEXT 640 312 Left 2 ;1 v/a
TEXT 968 416 Left 2 ;160 KHz
TEXT 696 560 Left 2 !.tran 2m
TEXT 752 88 Left 2 ;P902B
TEXT 680 136 Left 2 ;current limit concept
TEXT 704 184 Left 2 ;JL Nov 15 2020
TEXT 696 600 Left 2 !.param RL = 10
TEXT 696 640 Left 2 !.step param RL list 10 2 0.1
TEXT 448 48 Left 2 ;class-D power amp


--

John Larkin Highland Technology, Inc

Science teaches us to doubt.

Claude Bernard
 
On 15/11/2020 4:56 pm, jlarkin@highlandsniptechnology.com wrote:
I\'ve finished up the PCB design of my new class-D power amp, so now
the kids have to change the FPGA and ARM code to match. One problem is
current limiting. We have a current shunt on the amp output, but we
don\'t sense the voltage across the load.

We were brainstorming and simulating current limit schemes that we can
implement in the FPGA, which drives the DAC into my amp, and sees the
sensed load current. A hard clipper needs a lot of gain, and the
customer load is unknown, so a high-gain loop might be unstable.

So I was wondering (about 3 AM) how bad a low-gain clipper would be,
when it occurrs to me that a class-D amp has current gain from its
power supply into the load, so we can have a higher current limit at
low voltage out, for instance when the customer shorts our output.
It\'s an anti-foldback current limit in a system that can\'t sense the
output voltage.

This seems to work in an analog model. At any rate, it makes a cool
waveform at Isense. The current limit goes up when the load resistance
goes down. I\'m still trying to get my brain comfortable with that.
More coffee is indicated.

At the extreme implementation of anti-foldback, a graph of current
limit vs output voltage would be really strange, uuuuuu with spikes to
infinity.



Version 4
SHEET 1 1224 724
WIRE 1120 16 432 16
WIRE 432 64 432 16
WIRE -64 80 -128 80
WIRE 0 80 -64 80
WIRE 176 80 80 80
WIRE 288 80 176 80
WIRE 384 80 288 80
WIRE 1072 112 1024 112
WIRE 1120 112 1120 16
WIRE 1120 112 1072 112
WIRE 384 128 352 128
WIRE -128 144 -128 80
WIRE 176 160 176 80
WIRE 352 176 352 128
WIRE 432 176 432 144
WIRE 1120 176 1120 112
WIRE 176 288 176 224
WIRE 272 288 176 288
WIRE 432 288 352 288
WIRE 512 288 432 288
WIRE 672 288 592 288
WIRE 720 288 672 288
WIRE -128 304 -128 224
WIRE 720 352 720 288
WIRE 272 368 256 368
WIRE 304 368 272 368
WIRE 880 368 768 368
WIRE 976 368 880 368
WIRE 1120 368 1120 256
WIRE 1120 368 1056 368
WIRE 304 400 304 368
WIRE 880 400 880 368
WIRE 432 416 432 288
WIRE 432 416 336 416
WIRE 784 416 768 416
WIRE 176 432 176 288
WIRE 272 432 176 432
WIRE 432 448 336 448
WIRE 480 448 432 448
WIRE 496 448 480 448
WIRE 1120 448 1120 368
WIRE 720 464 720 432
WIRE 784 464 784 416
WIRE 784 464 720 464
WIRE -96 480 -128 480
WIRE -80 480 -96 480
WIRE 64 480 32 480
WIRE 80 480 64 480
WIRE 720 496 720 464
WIRE 880 496 880 464
WIRE -128 512 -128 480
WIRE 32 512 32 480
WIRE 272 512 256 512
WIRE 304 512 304 464
WIRE 304 512 272 512
WIRE 432 512 432 448
WIRE -128 640 -128 592
WIRE 32 640 32 592
WIRE 432 640 432 592
WIRE 1120 640 1120 528
FLAG -128 304 0
FLAG 432 640 0
FLAG -128 640 0
FLAG 32 640 0
FLAG -96 480 +5
FLAG 64 480 -5
FLAG 272 512 -5
FLAG 272 368 +5
FLAG 352 176 0
FLAG 432 176 0
FLAG 880 496 0
FLAG 1120 640 0
FLAG 720 496 0
FLAG -64 80 DDS
FLAG 288 80 CLIP
FLAG 480 448 LIM
FLAG 672 288 Isense
FLAG 1072 112 VOUT
SYMBOL res 96 64 R90
WINDOW 0 69 57 VBottom 2
WINDOW 3 74 59 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL diode 160 160 R0
WINDOW 0 -62 30 Left 2
WINDOW 3 -84 62 Left 2
SYMATTR InstName D1
SYMATTR Value 1N914
SYMBOL voltage -128 128 R0
WINDOW 0 37 102 Left 2
WINDOW 3 17 145 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdds
SYMATTR Value SINE(2.5 2.5 1K)
SYMBOL voltage 432 496 R0
WINDOW 0 57 38 Left 2
WINDOW 3 62 70 Left 2
SYMATTR InstName Vlim
SYMATTR Value 2.5
SYMBOL Opamps\\\\UniversalOpamp2 304 432 M0
WINDOW 0 -57 -53 Left 2
SYMATTR InstName U1
SYMBOL res 368 272 R90
WINDOW 0 -38 56 VBottom 2
WINDOW 3 -33 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL res 608 272 R90
WINDOW 0 -40 56 VBottom 2
WINDOW 3 -33 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL voltage -128 496 R0
WINDOW 0 51 37 Left 2
WINDOW 3 55 75 Left 2
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL voltage 32 496 R0
WINDOW 0 60 33 Left 2
WINDOW 3 59 69 Left 2
SYMATTR InstName V4
SYMATTR Value -5
SYMBOL e 432 48 R0
WINDOW 0 51 43 Left 2
WINDOW 3 68 76 Left 2
SYMATTR InstName Eamp
SYMATTR Value 10
SYMBOL res 1104 160 R0
WINDOW 0 -101 36 Left 2
WINDOW 3 -90 74 Left 2
SYMATTR InstName Rload
SYMATTR Value {RL}
SYMBOL res 1104 432 R0
WINDOW 0 -108 64 Left 2
WINDOW 3 -89 93 Left 2
SYMATTR InstName Rshunt
SYMATTR Value 1m
SYMBOL e 720 336 M0
WINDOW 0 74 48 Left 2
WINDOW 3 62 81 Left 2
SYMATTR InstName E2
SYMATTR Value 1000
SYMBOL res 1072 352 R90
WINDOW 0 -41 53 VBottom 2
WINDOW 3 -35 54 VTop 2
SYMATTR InstName R4
SYMATTR Value 1K
SYMBOL cap 864 400 R0
WINDOW 0 51 22 Left 2
WINDOW 3 49 51 Left 2
SYMATTR InstName C1
SYMATTR Value 1n
TEXT 640 312 Left 2 ;1 v/a
TEXT 968 416 Left 2 ;160 KHz
TEXT 696 560 Left 2 !.tran 2m
TEXT 752 88 Left 2 ;P902B
TEXT 680 136 Left 2 ;current limit concept
TEXT 704 184 Left 2 ;JL Nov 15 2020
TEXT 696 600 Left 2 !.param RL = 10
TEXT 696 640 Left 2 !.step param RL list 10 2 0.1
TEXT 448 48 Left 2 ;class-D power amp
Click to expand...

I can see you need output current sensing for metrology but for
protection and overload purposes isn\'t knowing the input current (from
the power supply) more useful?

piglet

Science teaches us to verify.
 
On Sun, 15 Nov 2020 19:44:15 +0000, piglet <erichpwagner@hotmail.com>
wrote:

On 15/11/2020 4:56 pm, jlarkin@highlandsniptechnology.com wrote:


I\'ve finished up the PCB design of my new class-D power amp, so now
the kids have to change the FPGA and ARM code to match. One problem is
current limiting. We have a current shunt on the amp output, but we
don\'t sense the voltage across the load.

We were brainstorming and simulating current limit schemes that we can
implement in the FPGA, which drives the DAC into my amp, and sees the
sensed load current. A hard clipper needs a lot of gain, and the
customer load is unknown, so a high-gain loop might be unstable.

So I was wondering (about 3 AM) how bad a low-gain clipper would be,
when it occurrs to me that a class-D amp has current gain from its
power supply into the load, so we can have a higher current limit at
low voltage out, for instance when the customer shorts our output.
It\'s an anti-foldback current limit in a system that can\'t sense the
output voltage.

This seems to work in an analog model. At any rate, it makes a cool
waveform at Isense. The current limit goes up when the load resistance
goes down. I\'m still trying to get my brain comfortable with that.
More coffee is indicated.

At the extreme implementation of anti-foldback, a graph of current
limit vs output voltage would be really strange, uuuuuu with spikes to
infinity.
Click to expand...

I can see you need output current sensing for metrology but for
protection and overload purposes isn\'t knowing the input current (from
the power supply) more useful?
Click to expand...

Into a short, a class-D amp can in theory furnish unlimited output
current from a tiny power supply current. Limiting power supply
current, from a fixed-voltage supply, is actually an output power
limit. I could make 50 amps and roast fets and magnetics using a
modest amount of DC input power.

Besides, I don\'t have an easy way to measure or limit power supply
current. Three amps share one 48 volt supply.

Here\'s a little better version, more down to basics.

https://www.dropbox.com/s/z1osf28jkknh4z5/P902B_Ilim1.jpg?raw=1

https://www.dropbox.com/s/rbobigy9u123ok3/P902B_Ilim_1.asc?dl=0


What\'s freaky is that this is an anti-foldback current limiter whose
two inputs are actual load current, and what the output voltage would
have been if it weren\'t loaded. Hurts my head.



--

John Larkin Highland Technology, Inc

Science teaches us to doubt.

Claude Bernard
 
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