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Hi,
In Cliff Cummings\'s paper \"Simulation and Synthesis Techniques for Asynchronous FIFO Design\" (at the web page: www.sunburst-design.com/papers), there is clear description on FULL/EMPTY design. As to almost_full/almost_empty, the author indicates to use the second adder after Gray-to-binary logic and use this value to substract rptr to get an almost_full signal. A less-than operation insures the almost_full is set for the full range.
I would like to generate almost_full/almost_empty with programmable settings, so I updated the design as these:
// -----------------------------------------------
// GRAYSTYLE2 pointer
always @(posedge wclk or negedge wrst_n) begin
if (!wrst_n)
{wbin, wptr} <= 0;
else
{wbin, wptr} <= {wbinnext, wgraynext};
end
always @(posedge wclk or negedge wrst_n) begin // this is added
if (!wrst_n)
wbin_p1 <= 0;
else
wbin_p1 <= wgraynextp1;
end
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + (winc & ~wfull);
assign wgraynext = (wbinnext >> 1) ^ wbinnext;
// this is added to generate the second adder
assign wgraynextp1 = ((wbinnext + prog_diff) >> 1) ^ (wbinnext + prog_diff);
assign wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
// this is added to generate almost_full
assign awfull_val = (wbin_p1 - wq2_rptr) <= prog_diff;
In my simulation I set prog_diff to 4. The fifo depth is set to 32. The simulation doesn\'t generate correct almost_full signal. Even in the start of the simulation, when fifo is start to write, almost_full is asserted.
It seems I can\'t generate the signal simply as what author indicated. Can anybody give me some suggestion? Thanks very much.
In Cliff Cummings\'s paper \"Simulation and Synthesis Techniques for Asynchronous FIFO Design\" (at the web page: www.sunburst-design.com/papers), there is clear description on FULL/EMPTY design. As to almost_full/almost_empty, the author indicates to use the second adder after Gray-to-binary logic and use this value to substract rptr to get an almost_full signal. A less-than operation insures the almost_full is set for the full range.
I would like to generate almost_full/almost_empty with programmable settings, so I updated the design as these:
// -----------------------------------------------
// GRAYSTYLE2 pointer
always @(posedge wclk or negedge wrst_n) begin
if (!wrst_n)
{wbin, wptr} <= 0;
else
{wbin, wptr} <= {wbinnext, wgraynext};
end
always @(posedge wclk or negedge wrst_n) begin // this is added
if (!wrst_n)
wbin_p1 <= 0;
else
wbin_p1 <= wgraynextp1;
end
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + (winc & ~wfull);
assign wgraynext = (wbinnext >> 1) ^ wbinnext;
// this is added to generate the second adder
assign wgraynextp1 = ((wbinnext + prog_diff) >> 1) ^ (wbinnext + prog_diff);
assign wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
// this is added to generate almost_full
assign awfull_val = (wbin_p1 - wq2_rptr) <= prog_diff;
In my simulation I set prog_diff to 4. The fifo depth is set to 32. The simulation doesn\'t generate correct almost_full signal. Even in the start of the simulation, when fifo is start to write, almost_full is asserted.
It seems I can\'t generate the signal simply as what author indicated. Can anybody give me some suggestion? Thanks very much.