ADCs in FPGAs...

[David Brown]

On 24/10/2020 10:24, Michael Kellett wrote:

On 24/10/2020 05:30, Rick C wrote:
On Friday, October 23, 2020 at 5:00:38 PM UTC-4,

if you need to add external parts you might as well add a real adc

Not all parts are the same.  The ADCs that give more than 12 bits on
multiple channels are in the $5 and up range.  I can get comparators
for a quarter and CMOS buffers for a dime.  I\'m not sure the
comparators are needed.  The buffer might help though.


You are  a bit out on price, you can buy an 8 channel part from
Microchip at about $3 5k off, MCP3464 (16 bit, 8 single ended or 4
differential channels).
That way you get a fully sorted part with with built in PGA and you
won\'t be at the mercy of using unspecified performance of the FPGA.

It is also going to be dependent on the tolerances of the other parts -
the resistors, capacitors, buffers.

It would save you endless heartache in approval and
certification/qualification time - I certainly wouldn\'t want to get
involved with the FMEA for the FPGA sigma-delta design.

There may well be cheaper parts than this.

There are also lots of microcontrollers with quite reasonable
multi-channel ADC\'s and lower prices than this. They are usually not so
good for high resolution, but you can do other things with the
microcontroller too.

And for higher resolution requirements, the effort to make your own and
be sure it is accurate would seem ridiculous. How many hundreds of
thousands of systems are you making where the development costs of
rolling your own ADC, testing and qualifying it save the cost of buying one?

 

[Mike Perkins]

On 24/10/2020 07:08:17, Rick C wrote:

On Friday, October 23, 2020 at 9:00:37 PM UTC-4, Mike Perkins wrote:
On 23/10/2020 19:07:53, Rick C wrote:
On Friday, October 23, 2020 at 3:02:53 AM UTC-4, Stef wrote:
On 2020-10-23 Rick C wrote in comp.arch.fpga:

Someone said they had used an instantiated ADC in the Xilinx
tools. Anyone know if that is actually an ADC or if it is an
ADC chip interface?

On what Xilinx device? At least the Zynq devices do have
actual ADC\'s.

Don\'t know yet. I\'m asking questions, but he specifically said
instantiated \"IP\" but I suppose that might be the same as
\"instantiating\" a clock block with PLL ect.

I\'m essentially interviewing him to work on this open source
project and the real issue is how much he knows about delta-sigma
converters and how to implement them.

Right now I\'d like to get an idea of whether it would
significantly improve accuracy and/or noise to use separate
comparator and driver for the analog interface. The sensors are
powered from 5 volts and so produce a 5 volt analog output. The
separate drivers and comparators could be powered from the same
supply, separate from any other supply on the board for noise
isolation. Also, as the sensor outputs are proportional to the
power rail voltage, this will make all measurements ratiometric
eliminating the need to correct for the power voltages.
Otherwise we need to provide the I/O bank 3.3 volts that is a
ratioed to the 5 volt rail. I guess no big deal. The point is
it\'s not that much more to use separate comparators and drivers
and may get us noise and accuracy advantages.

Sorry if this sounds irrelevant. I often uses newsgroup posts
to solidify my thinking. In this case we have tons of I/Os
available, so I think I\'m going to use both approaches and
dedicate a bank of I/Os to the ADCs.

Nothing wrong with thinking out loud.

Like another poster has suggested, and unless there is a tight
budget in terms of space or money, it can be cost effective in
terms of design time (and cost) to simply fit a known ADC to the
PCB that has a known spec and reduce overall risk.

There will be a socket on the board for an ADC chip. I\'m not going
to risk a board spin just for this idea. Risk mitigation. But at $5
each significant money can be saved in production by using an
integrated ADC in the FPGA.

Sounds like best of both worlds.

We actually don\'t need more than 10 bits for anything other than one
sensor that will spend most of it\'s time in the very low end of the
range. If I can get 12 useful bits we are probably ok. Using a
single slope converter with calibration by measuring a Vref I can
probably get better resolution at the low end and still have good
results with the simpler circuit.

That\'s still only a few mV of noise threshold.

I\'m not sure how much \"noise\" will be a problem. The absolute
accuracy is limited by the sensors to a couple percent. But we need
good resolution for the control loop and for the flow rate which we
are integrating into a volume.

Sometimes I talk myself into this being a snap and other times I
worry it won\'t work worth a damn.

The delta-sigma circuits can be designed so they can be built to work
with a mid-scale Vref and then allow for a single slope configuration
with a common slope circuit. I was planning on using something like
the single slope converter with the slower signals anyway. I should
probably design something so it can be tested without involving the
sensors since it will be hard to manipulate them to get a particular
output voltage.

I might use a standard comparator rather than rely on an input with a
noisy threshold. Not mentioning the violation of rise times.

Or I can convince the group we should use digital sensors. Lol! Not
sure why we picked analog sensors. I\'m having trouble finding anyone
who carries stock on a board mounted differential pressure sensor
other than the one we are using. The gage pressure sensor is
available with a digital output though. Only $10.

My experience of off-board third party digital sensors isn\'t a happy one
with I2C sensors locking up on a glitch and having to reset them on the fly.

YMMV



--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

 

[Rick C]

On Saturday, October 24, 2020 at 4:24:31 AM UTC-4, Michael Kellett wrote:

On 24/10/2020 05:30, Rick C wrote:
On Friday, October 23, 2020 at 5:00:38 PM UTC-4, lasselangwad...@gmail.com wrote:
fredag den 23. oktober 2020 kl. 20.07.58 UTC+2 skrev Rick C:
On Friday, October 23, 2020 at 3:02:53 AM UTC-4, Stef wrote:
On 2020-10-23 Rick C wrote in comp.arch.fpga:

Someone said they had used an instantiated ADC in the Xilinx tools. Anyone know if that is actually an ADC or if it is an ADC chip interface?

On what Xilinx device? At least the Zynq devices do have actual ADC\'s.

Don\'t know yet. I\'m asking questions, but he specifically said instantiated \"IP\" but I suppose that might be the same as \"instantiating\" a clock block with PLL ect.

I\'m essentially interviewing him to work on this open source project and the real issue is how much he knows about delta-sigma converters and how to implement them.

Right now I\'d like to get an idea of whether it would significantly improve accuracy and/or noise to use separate comparator and driver for the analog interface. The sensors are powered from 5 volts and so produce a 5 volt analog output. The separate drivers and comparators could be powered from the same supply, separate from any other supply on the board for noise isolation. Also, as the sensor outputs are proportional to the power rail voltage, this will make all measurements ratiometric eliminating the need to correct for the power voltages. Otherwise we need to provide the I/O bank 3.3 volts that is a ratioed to the 5 volt rail. I guess no big deal. The point is it\'s not that much more to use separate comparators and drivers and may get us noise and accuracy advantages.

Sorry if this sounds irrelevant. I often uses newsgroup posts to solidify my thinking. In this case we have tons of I/Os available, so I think I\'m going to use both approaches and dedicate a bank of I/Os to the ADCs.


if you need to add external parts you might as well add a real adc

Not all parts are the same. The ADCs that give more than 12 bits on multiple channels are in the $5 and up range. I can get comparators for a quarter and CMOS buffers for a dime. I\'m not sure the comparators are needed.. The buffer might help though.


You are a bit out on price, you can buy an 8 channel part from
Microchip at about $3 5k off, MCP3464 (16 bit, 8 single ended or 4
differential channels).
That way you get a fully sorted part with with built in PGA and you
won\'t be at the mercy of using unspecified performance of the FPGA.

It would save you endless heartache in approval and
certification/qualification time - I certainly wouldn\'t want to get
involved with the FMEA for the FPGA sigma-delta design.

There may well be cheaper parts than this.

Which aspects of the FPGA impact the performance of a delta-sigma ADC? Or even a single slope ADC? The only relevant aspect would be the voltage drop from Vcc/ground to the output drive which is going to be very small when driving low currents.

As I said, there will be an ADC on board for testing. Then we will choose the method that works best for our goals.

No risk, no worries.

If anything, having the delta-sigma ADC as a backup to the chip ADC reduces the risk if there is a glitch with the chip. It\'s not like ICs never have problems.

$0.10 is still a lot better than $3.50.

--

Rick C.

+-- Get 1,000 miles of free Supercharging
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[gnuarm.del...@gmail.com]

I\'ve been messing with this for a bit and the ultimate limitation seems to me to not be the digital noise in the FPGA, but rather the imbalance in the edge rise/fall times and/or propagation delays.

The digital noise in the FPGA is going to be mostly in the core. The I/Os are the part that matter to the analog portion of the ADC and they have separate Vcco from the core and also one another. I\'ve been planning to dedicate a bank to the ADCs. But the input signals have a 5 volt range and will require a 3.3 Vcco that is ratiometric to the 5 volt supply. It seems simpler to add a 5 volt level shifter and let that be powered by the sensor 5 volt rail.

So now I\'m looking for the right buffer device and I\'m starting to realize the limitation is the symmetry in the rise/fall times and the propagation delays of the two edges. Buffers are not so good with this having delays of single digit ns, but also lack of symmetry of single digit ns. With 30 ns pulses, that would add up. I thought analog switches might be better, but they are worse with unbalanced switching times being hard to get into the low single digit ns. Many of the parts I find are LVC which require 3.3 volt power to get compatible input levels. I guess that\'s what the L is for in LVC, duh!

Anyone know of parts that would be good for this? Would it make sense to run through two buffers at least conceptually balancing the rise/fall times and prop delays? But then the delays start to add up, but that probably doesn\'t matter as much.

I found the 74ACT244 which seems to be the best fit so far. 5V power, TTL inputs to be compatible with 3.3V CMOS, balanced HL and LH propagation times and balanced H and L drive capabilities. The prop delay can be up to 9 ns which is a significant portion of the 30 ns cycle time, but that should not be a significant factor.

--

Rick C.

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